Intel Xeon E5540 P4X-DPE5540-253-8M586 User Manual

Product codes

P4X-DPE5540-253-8M586

Intel

Xeon

Processor 5500 Series Datasheet, Volume 1

133

Features

‘C-state Range’ field. This field maybe written by BIOS to restrict the range of I/O
addresses that are trapped and redirected to MWAIT instructions. Note that when I/O
instructions are used, no MWAIT substates can be defined, as therefore the request
defaults to have a sub-state or zero, but always assumes the ‘break on EFLAGS.IF==0’
control that can be selected using ECX with an MWAIT instruction.

7.2.1

Thread and Core Power State Descriptions

Individual threads may request low power states as described below. Core power states
are automatically resolved by the processor as shown in

Table 7-2

Notes:

If enabled, state will be C1E.

7.2.1.1

C0 State

This is the normal operating state in the processor.

Figure 7-2. Power States

1. No transition to C0 is needed to service a snoop when in C1 or C1E.

2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was entered via MWAIT).

C E

MWAIT C1,

HLT

MWAIT C1,

HLT (C1E

enabled)

MWAIT C6,

I/O C6

MWAIT C3,

I/O C3

Table 7-2.

Coordination of Thread Power States at the Core Level

Core State

Thread 1 State

Thread 0 State