Motorola MPC8260 User Manual

2-14

MOTOROLA

2.3.1.2.2  Hardware Implementation-Dependent Register 1 (HID1)
The MPC8260 implementation of HID1 is shown in Figure 2-4. 

20

ICFI

Instruction cache ßash invalidate 

2

0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation 

begins (usually the next cycle after the write operation to the register). The instruction cache 
must be enabled for the invalidation to occur. 

1 An invalidate operation is issued that marks the state of each instruction cache block as invalid 

without writing back modiÞed cache blocks to memory. Cache access is blocked during this 
time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. 
Setting ICFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each 
set. Once the L1 ßash invalidate bits are set through an mtspr instruction, hardware 
automatically resets these bits in the next cycle (provided that the corresponding cache 
enable bits are set in HID0).

21

DCFI

Data cache ßash invalidate 

2

0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins 

(usually the next cycle after the write operation to the register). The data cache must be 
enabled for the invalidation to occur. 

1 An invalidate operation is issued that marks the state of each data cache block as invalid 

without writing back modiÞed cache blocks to memory. Cache access is blocked during this 
time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. 
Setting DCFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each 
set. Once the L1 ßash invalidate bits are set through an mtspr instruction, hardware 
automatically resets these bits in the next cycle (provided that the corresponding cache 
enable bits are set in HID0).

22Ð23

Ñ

Reserved

24

IFEM

Enable M bit on 60x bus for instruction fetches
0 M bit not reßected on 60x bus. Instruction fetches are treated as nonglobal on the bus.
1 Instruction fetches reßect the M bit from the WIM settings on the 60x bus. 

25Ð26

Ñ

Reserved

27

FBIOB

Force branch indirect on bus. 
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally.

28

ABE

Address broadcast enable 
0  dcbf, dcbi, and dcbst instructions are not broadcast on the 60x bus. 
1  dcbf, dcbi, and dcbst generate address-only broadcast operations on the 60x bus.

29Ð30

Ñ

Reserved

31

NOOPTI

No-op the data cache touch instructions.
0 The dcbt and dcbtst instructions are enabled. 
1 The dcbt and dcbtst instructions are no-oped globally. 

1

 See Chapter 9, ÒPower Management,Ó of the MPC603e UserÕs Manual for more information.

2

 See Chapter 3, ÒInstruction and Data Cache Operation,Ó of the MPC603e UserÕs Manual for more information.