Motorola MPC8260 User Manual
MOTOROLA
Chapter 2. PowerPC Processor Core
2-19
Part I. Overview
PowerPC microprocessors control the following memory access modes on a page or block
basis:
basis:
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Write-back/write-through mode
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Caching-inhibited mode
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Memory coherency
The PowerPC cache management instructions provide a means by which the application
programmer can affect the cache contents.
programmer can affect the cache contents.
2.4.2 MPC8260 Implementation-SpeciÞc Cache Implementation
As shown in Figure 2-1, the caches provide a 64-bit interface to the instruction fetch unit
and load/store unit. The surrounding logic selects, organizes, and forwards the requested
information to the requesting unit. Write operations to the cache can be performed on a byte
basis, and a complete read-modify-write operation to the cache can occur in each cycle.
and load/store unit. The surrounding logic selects, organizes, and forwards the requested
information to the requesting unit. Write operations to the cache can be performed on a byte
basis, and a complete read-modify-write operation to the cache can occur in each cycle.
Each cache block contains eight contiguous words from memory that are loaded from an
8-word boundary (that is, bits A27ÐA31 of the effective addresses are zero); thus, a cache
block never crosses a page boundary. Misaligned accesses across a page boundary can incur
a performance penalty.
8-word boundary (that is, bits A27ÐA31 of the effective addresses are zero); thus, a cache
block never crosses a page boundary. Misaligned accesses across a page boundary can incur
a performance penalty.
The cache blocks are loaded in to the processor core in four beats of 64 bits each. The burst
load is performed as critical double word Þrst.
load is performed as critical double word Þrst.
To ensure coherency among caches in a multiprocessor (or multiple caching-device)
implementation, the processor core implements the MEI protocol. These three states,
modiÞed, exclusive, and invalid, indicate the state of the cache block as follows:
implementation, the processor core implements the MEI protocol. These three states,
modiÞed, exclusive, and invalid, indicate the state of the cache block as follows:
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ModiÞedÑThe cache block is modiÞed with respect to system memory; that is, data
for this address is valid only in the cache and not in system memory.
for this address is valid only in the cache and not in system memory.
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ExclusiveÑThis cache block holds valid data that is identical to the data at this
address in system memory. No other cache has this data.
address in system memory. No other cache has this data.
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InvalidÑThis cache block does not hold valid data.
2.4.2.1 Data Cache
As shown in Figure 2-6, the data cache is conÞgured as 128 sets of four blocks each. Each
block consists of 32 bytes, two state bits, and an address tag. The two state bits implement
the three-state MEI (modiÞed/exclusive/invalid) protocol. Each block contains eight 32-bit
words. Note that the PowerPC architecture deÞnes the term ÔblockÕ as the cacheable unit.
For the MPC8260Õs processor core, the block size is equivalent to a cache line.
block consists of 32 bytes, two state bits, and an address tag. The two state bits implement
the three-state MEI (modiÞed/exclusive/invalid) protocol. Each block contains eight 32-bit
words. Note that the PowerPC architecture deÞnes the term ÔblockÕ as the cacheable unit.
For the MPC8260Õs processor core, the block size is equivalent to a cache line.