Motorola MPC8260 User Manual
MOTOROLA
Chapter 4. System Interface Unit (SIU)
4-3
Part II. ConÞguration and Reset
Figure 4-2. System Configuration and Protection Logic
Many aspects of system conÞguration are controlled by several SIU module conÞguration
registers, described in Section 4.3.2, ÒSystem ConÞguration and Protection Registers.Ó
registers, described in Section 4.3.2, ÒSystem ConÞguration and Protection Registers.Ó
4.1.1 Bus Monitor
The MPC8260 has two bus monitors, one for the 60x bus and one for the local bus. The bus
monitor ensures that each bus cycle is terminated within a reasonable period. The bus
monitor does not count when the bus is idle. When a transaction starts (TS asserted), the
bus monitor starts counting down from the time-out value. For standard bus transactions
with an address tenure and a data tenure, the bus monitor counts until a data beat is
acknowledged on the bus. It then reloads the time-out value and resumes the count down.
This process continues until the whole data tenure is completed. Following the data tenure
the bus monitor will idle in case there is no pending transaction; otherwise it will reload the
time-out value and resume counting.
monitor ensures that each bus cycle is terminated within a reasonable period. The bus
monitor does not count when the bus is idle. When a transaction starts (TS asserted), the
bus monitor starts counting down from the time-out value. For standard bus transactions
with an address tenure and a data tenure, the bus monitor counts until a data beat is
acknowledged on the bus. It then reloads the time-out value and resumes the count down.
This process continues until the whole data tenure is completed. Following the data tenure
the bus monitor will idle in case there is no pending transaction; otherwise it will reload the
time-out value and resume counting.
For address-only transactions, the bus monitor counts until AACK is asserted. If the
monitor times out for a standard bus transaction, transfer error acknowledge (TEA) is
asserted. If the monitor times out for an address-only transaction, the bus monitor asserts
AACK and a core machine check or reset interrupt is generated, depending on
SYPCR[SWRI]. To allow variation in system peripheral response times, SYPCR[BMT]
deÞnes the time-out period, whose maximum value can be 2,040 system bus clocks. The
timing mechanism is clocked by the system bus clock divided by eight.
monitor times out for a standard bus transaction, transfer error acknowledge (TEA) is
asserted. If the monitor times out for an address-only transaction, the bus monitor asserts
AACK and a core machine check or reset interrupt is generated, depending on
SYPCR[SWRI]. To allow variation in system peripheral response times, SYPCR[BMT]
deÞnes the time-out period, whose maximum value can be 2,040 system bus clocks. The
timing mechanism is clocked by the system bus clock divided by eight.
Module
Configuration
Bus
Monitors
Periodic Interrupt
Timer
Software
Watchdog Timer
Time
Counter
TEA
Interrupt
CoreÕs MCP
Interrupt
CoreÕs MCP
System Reset
timersclk
Bus Clock
timersclk
System Reset
Bus clock/8