Motorola MPC8260 User Manual

MOTOROLA

Chapter 4.  System Interface Unit (SIU)  

4-9

If the software watchdog timer is programmed to generate an interrupt, it always generates
a machine check interrupt to the core. The external IRQ0 can generate MCP as well. Note
that the core takes the machine check interrupt when MCP is asserted; it takes an external
interrupt for any other interrupt asserted by the interrupt controller. 

The interrupt controller allows masking of each interrupt source. Multiple events within a
CPM sub-block event are also maskable.

All interrupt sources are prioritized and bits are set in the interrupt pending register
(SIPNR). On the MPC8260, the prioritization of the interrupt sources is ßexible in the
following two aspects:

¥

The relative priority of the FCCs, SCCs, and MCCs can be modiÞed

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One interrupt source can be assigned the highest priority 

When an unmasked interrupt source is pending in the SIPNR, the interrupt controller sends
an interrupt request to the core. When an exception is taken, the interrupt mask bit in the
machine state register (MSR[EE]) is cleared to disable further interrupt requests until
software can handle them. 

The SIU interrupt vector register (SIVEC) is updated with a 6-bit vector corresponding to
the sub-block with the highest current priority. 

The interrupt controller has 37 interrupt sources that assert one interrupt request to the core.
Table 4-2 shows prioritization of all interrupt sources. As described in following sections,
ßexibility exists in the relative ordering of the interrupts, but, in general, relative priorities
are as shown. A single interrupt priority number is associated with each table entry. 

Note that the group and spread options, shown with YCC entries in Table 4-2, are described
in Section 4.2.2.1, ÒSCC, FCC, and MCC Relative Priority.Ó

1

Highest

Ñ

2

XSIU1 

No (TMCNT,PIT = Yes)

3

XSIU2 (GSIU = 0)

No (TMCNT,PIT = Yes)

4

XSIU3 (GSIU = 0)

No (TMCNT,PIT = Yes)