Motorola MPC8260 User Manual
4-24
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part II. ConÞguration and Reset
The SIVEC can be read as either a byte, half word, or a word. When read as a byte, a branch
table can be used in which each entry contains one instruction (branch). When read as a half
word, each entry can contain a full routine of up to 256 instructions. The interrupt code is
deÞned such that its two lsbs are zeroes, allowing indexing into the table, as shown in
Figure 4-19.
table can be used in which each entry contains one instruction (branch). When read as a half
word, each entry can contain a full routine of up to 256 instructions. The interrupt code is
deÞned such that its two lsbs are zeroes, allowing indexing into the table, as shown in
Figure 4-19.
Figure 4-19. Interrupt Table Handling Example
Note that the MPC8260 differs from previous MPC8xx implementations in that when an
interrupt request occurs, SIVEC can be read. If there are multiple interrupt sources, SIVEC
latches the highest priority interrupt. Note that the value of SIVEC cannot change while it
is being read.
interrupt request occurs, SIVEC can be read. If there are multiple interrupt sources, SIVEC
latches the highest priority interrupt. Note that the value of SIVEC cannot change while it
is being read.
4.3.1.7 SIU External Interrupt Control Register (SIEXR)
Each deÞned bit in the SIU external interrupt control register (SIEXR), shown in
Figure 4-20, determines whether the corresponding port C line asserts an interrupt request
upon either a high-to-low change or any change on the pin. External interrupts can come
from port C (PC[0-15]).
Figure 4-20, determines whether the corresponding port C line asserts an interrupt request
upon either a high-to-low change or any change on the pin. External interrupts can come
from port C (PC[0-15]).
BASE
b Routine1
b Routine2
b Routine3
b Routine4
•
•
BASE + n
BASE + 4
BASE + 8
BASE + C
BASE +10
BASE
1st Instruction of Routine1
1st Instruction of Routine2
1st Instruction of Routine3
1st Instruction of Routine4
•
•
BASE + n
BASE + 400
BASE + 800
BASE + C00
BASE +1000
•
•
•
•
•
•
INTR: ¥ ¥ ¥
Save state
R3 <- @ SIVEC
R4 <-- Base of branch table
¥ ¥ ¥
lbz
add
mtspr
bctr
RX, R3 (0)
# load as byte
RX, RX, R4
CTR, RX
INTR: ¥ ¥ ¥
Save state
R3 <- @ SIVEC
R4 <-- Base of branch table
¥ ¥ ¥
lhz
add
mtspr
bctr
RX, R3 (0)
# load as half
RX, RX, R4
CTR, RX