Motorola MPC8260 User Manual
4-37
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part II. ConÞguration and Reset
4.3.2.11 60x Bus Transfer Error Status and Control Register 2
(TESCR2)
The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32.
6
EXT
External error. Indicates that TEA was asserted by an external bus slave.
7Ð9
TC
Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA. See
Section 8.4.3.2, ÒTransfer Code Signals TC[0Ð2],Ó for a description of the various transfer codes.
Section 8.4.3.2, ÒTransfer Code Signals TC[0Ð2],Ó for a description of the various transfer codes.
10
Ñ
Reserved, should be cleared.
11Ð15
TT
Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA.
See Section 8.4.3.1, ÒTransfer Type Signal (TT[0Ð4]) Encoding,Ó for a description of the various
transfer types.
See Section 8.4.3.1, ÒTransfer Type Signal (TT[0Ð4]) Encoding,Ó for a description of the various
transfer types.
16
Ñ
Reserved, should be cleared.
17
DMD
Data errors disable.
0 Errors are enabled.
1 All data errors (parity and single and double ECC errors) on the 60x bus are disabled.
0 Errors are enabled.
1 All data errors (parity and single and double ECC errors) on the 60x bus are disabled.
18Ð23
Ñ
Reserved, should be cleared.
24Ð31 ECNT Single ECC error counter.Indicates the number of single ECC errors that occurred in the system.
When the counter reaches its maximum value (255), TEA is asserted for all single ECC errors. This
feature gives the system the ability to withstand a few random errors yet react to a catastrophic failure.
The user can set a lower threshold to the number of tolerated single ECC errors by writing some value
to ECNT. The counter starts from this value instead of zero.
feature gives the system the ability to withstand a few random errors yet react to a catastrophic failure.
The user can set a lower threshold to the number of tolerated single ECC errors by writing some value
to ECNT. The counter starts from this value instead of zero.
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
REGS
DPR
Ñ
LCL
PB
Reset
0000_0000_0000_0000
R/W
R/W
Addr
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
BNK
Ñ
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x10046
Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
Table 4-15. TESCR1 Field Descriptions (Continued)
Bits
Name
Description