Motorola MPC8260 User Manual
MOTOROLA
Chapter 5. Reset
5-5
Part II. ConÞguration and Reset
Note that RSR accumulates reset events. For example, because software watchdog
expiration results in a hard reset, which in turn results in a soft reset, RSR[SWRS],
RSR[ESRS] and RSR[EHRS] are all set after a software watchdog reset.
expiration results in a hard reset, which in turn results in a soft reset, RSR[SWRS],
RSR[ESRS] and RSR[EHRS] are all set after a software watchdog reset.
5.3 Reset Mode Register (RMR)
The reset mode register (RMR), shown in Figure 5-2, is memory-mapped into the SIU
register map.
register map.
30
ESRS
External soft reset status. When an external soft reset event is detected, ESRS is set and it remains
that way until software clears it. ESRS is cleared by writing a 1 to it (writing zero has no effect).
0 No external soft reset event has occurred
1 An external soft reset event has occurred
that way until software clears it. ESRS is cleared by writing a 1 to it (writing zero has no effect).
0 No external soft reset event has occurred
1 An external soft reset event has occurred
31
EHRS
External hard reset status. When an external hard reset event is detected, EHRS is set and it
remains set until software clears it. EHRS is cleared by writing a 1 (writing zero has no effect).
0 No external hard reset event has occurred
1 An external hard reset event has occurred
remains set until software clears it. EHRS is cleared by writing a 1 (writing zero has no effect).
0 No external hard reset event has occurred
1 An external hard reset event has occurred
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
R/W
R/W
Reset
0000_0000_0000_0000
Addr
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Ñ
CSRE
R/W
R/W
Reset
0000_0000_0000_0000
Addr
0x10C96
Figure 5-2. Reset Mode Register (RMR)
Table 5-4. RMR Field Descriptions
Bits
Name
Function
0Ð30
Ñ
Reserved, should be cleared.
31
CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception
conditions. Setting CSRE conÞgures the chip to perform a hard reset sequence whenever the core
enters checkstop state.
0 Reset not generated when core enters checkstop state.
1 Reset generated when core enters checkstop state.
enters checkstop state.
0 Reset not generated when core enters checkstop state.
1 Reset generated when core enters checkstop state.
Table 5-3. RSR Field Descriptions (Continued)
Bits
Name
Function