Motorola MPC8260 User Manual

Part III-ii

MOTOROLA

This section lists additional reading that provides background for the information in this
manual as well as general information about the PowerPC architecture. 

Supporting documentation for the MPC8260 can be accessed through the world-wide web
at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical
speciÞcations, reference materials, and detailed applications notes.

The PowerPC documentation is organized in the following types of documents:

PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors 
(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of 
the 60x bus interface, as implemented on the PowerPC MPC601ª, MPC603, 
MPC604, and MPC750 family of PowerPC microprocessors. This document is 
intended to help system and chip set developers by providing a centralized reference 
source to identify the bus interface presented by the 60x family of PowerPC 
microprocessors.

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Application notesÑThese short documents contain useful information about 
speciÞc design issues useful to programmers and engineers working with PowerPC 
processors. 

For a current list of PowerPC documentation, refer to the world-wide web at 
http://www.mot.com/PowerPC.

This document uses the following notational conventions:

Bold entries in Þgures and tables showing registers and parameter 
RAM should be initialized by the user. 

Instruction mnemonics are shown in lowercase bold. 

Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.

0x0

PreÞx to denote hexadecimal number

0b0

PreÞx to denote binary number

REG[FIELD]

Abbreviations or acronyms for registers or buffer descriptors are 
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges 
appear in brackets. For example, MSR[LE] refers to the little-endian 
mode enable bit in the machine state register.

x

In certain contexts, such as in a signal encoding or a bit Þeld, 
indicates a donÕt care.