Motorola MPC8260 User Manual
MOTOROLA
Chapter 10. Memory Controller
10-9
Part III. The Hardware Interface
10.2.2 Page Hit Checking
The SDRAM machine supports page-mode operation. Each time a page is activated on the
SDRAM device, the SDRAM machine stores its address in a page register. The page
information, which the user writes to the ORx register, is used along with the bank size to
compare page bits of the address to the page register each time a bus-cycle access is
requested. If a match is found together with bank match, the bus cycle is deÞned as a page
hit. An open page is automatically closed by the SDRAM machine if the bus becomes idle,
unless ORx[PMSEL] is set.
SDRAM device, the SDRAM machine stores its address in a page register. The page
information, which the user writes to the ORx register, is used along with the bank size to
compare page bits of the address to the page register each time a bus-cycle access is
requested. If a match is found together with bank match, the bus cycle is deÞned as a page
hit. An open page is automatically closed by the SDRAM machine if the bus becomes idle,
unless ORx[PMSEL] is set.
10.2.3 Error Checking and Correction (ECC)
ECC can be conÞgured for any bank as long as it is assigned to the 60x bus and is connected
to a 64-bit port size memory. ECC is generated and checked on a 64-bit basis using DP[0Ð7]
for the bank if BRx[DECC] = 11. If ECC is used, single errors can be corrected and all
double-bit errors can be detected.
to a 64-bit port size memory. ECC is generated and checked on a 64-bit basis using DP[0Ð7]
for the bank if BRx[DECC] = 11. If ECC is used, single errors can be corrected and all
double-bit errors can be detected.
10.2.4 Parity Generation and Checking
Parity can be conÞgured for any bank, if it is preferred. Parity is generated and checked on
a per-byte basis using DP[0Ð7] or LDP[0Ð3] for the bank if BR[DECC] = 01 for normal
parity and 10 for RMW parity. SIUMCR[EPAR] determines the global type of parity (odd
or even).
a per-byte basis using DP[0Ð7] or LDP[0Ð3] for the bank if BR[DECC] = 01 for normal
parity and 10 for RMW parity. SIUMCR[EPAR] determines the global type of parity (odd
or even).
Note that RMW parity can be used only for 32- or 64-bit port size banks. Also, using RMW
parity on a 32-bit port size bank, requires that the bus is placed is strict 60x mode. This is
done by setting BCR[ETM] (BCR[LETM] for the local bus) see Section 4.3.2.1, ÒBus
ConÞguration Register (BCR),Ó for more details.
parity on a 32-bit port size bank, requires that the bus is placed is strict 60x mode. This is
done by setting BCR[ETM] (BCR[LETM] for the local bus) see Section 4.3.2.1, ÒBus
ConÞguration Register (BCR),Ó for more details.
10.2.5 Transfer Error Acknowledge (TEA) Generation
The memory controller asserts the transfer error acknowledge signal (TEA) (if enabled) in
the following cases:
the following cases:
¥
An unaligned or burst access is attempted to internal MPC8260 space (registers or
dual-port RAM).
dual-port RAM).
¥
The core or an external master attempts a burst access to the local bus address space
¥
A bus monitor timeout
10.2.6 Machine Check Interrupt (MCP) Generation
The memory controller asserts machine check interrupt (MCP) in the following cases:
¥
A parity error
¥
An ECC double-bit error
¥
An ECC single bit error when the maximum number of ECC errors has been reached