Motorola MPC8260 User Manual

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MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
10.3.11  Local Bus-Assigned SDRAM Refresh Timer (LSRT)
The local bus-assigned SDRAM refresh timer register (LSRT) is shown in Figure 10-17. 
10.3.12  Memory Refresh Timer Prescaler Register (MPTPR)
Figure 10-18 shows the memory refresh timer prescaler register (MPTPR). 
Bit
0
1
2
3
4
5
6
7
Field
LSRT
Reset
0000_0000
R/W
R/W
Addr
Figure 10-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT)
Table 10-15. LSRT Field Descriptions
Bits
Name
Description
0Ð7
LSRT
Refresh timer period. Determines the timer period according to the following equation:
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned 
to the local bus and is refresh enabled (LSDMR[RFEN] = 1). Each time the timer expires, all banks 
that qualify generate a bank staggering auto refresh request using the SDRAM machine. See 
Section 10.4.10, ÒSDRAM Refresh.Ó 
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given 
MPTPR[PTP] = 32, the LSRT value should be 12 (decimal). 12/(25 MHz/32) = 15.36 µs, which is less 
than the required service period of 15.6 µs.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
PTP
Ñ
Reset
0000_001x 0000_0000
R/W
R/W
Addr
Figure 10-18. Memory Refresh Timer Prescaler Register (MPTPR)
Table 10-16. MPTPR Field Descriptions
Bits
Name
Description
0Ð7
PTP
Refresh timers prescaler. Determines the period of the memory refresh timers input clock. It divides 
the system clock.
8Ð15
Ñ
Reserved, should be cleared
TimerPeriod
LSRT
F
MPTC
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