Motorola MPC8260 User Manual

10-36

MOTOROLA

The SDRAM interface supports back-to-back page mode. A page remains open as long as
back-to-back accesses that hit the page are generated on the bus. The page is closed once
the bus becomes idle unless ORx[PMSEL] is set.

The use of SDRAM pipelining allows data phases to occur on with zero bubbles for CPM
accesses and with one bubble for core accesses, as required by the 60x bus speciÞcation.

If ETM/LETM = 1, the use of SDRAM pipelining also allows for back-to-back data 
phases to occur with zero clocks of separation for CPM accesses and with one clock of 
separation for core accesses, as required by the 60x bus speciÞcation.

The SDRAM interface supports bank interleaving. This means that if a missed page is in a
different SDRAM bank than the currently open page, the SDRAM machine Þrst issues an

ACTIVATE

 command to the new page and later issues a 

DEACTIVATE

 command to the old

page, thus eliminating the 

DEACTIVATE

 time overhead.

This procedure can be done if both pages reside on different SDRAM devices or on
different internal SDRAM banks. The second option can be disabled by setting ORx[IBID].
The user should set this bit if the BNKSEL pins are not used in 60x-compatible mode.

PRECHARGE

 

(

SINGLE

 

BANK

/

ALL

 

BANKS

)

Restores data from the sense ampliÞers to the appropriate row. Also initializes the sense ampliÞers to 
prepare for reading another row in the SDRAM array. A 

PRECHARGE

 command must be issued after a 

read or write if the row address changes on the next access. Note that the MPC8260 uses the SDA10 
pin to distinguish the 

PRECHARGE

-

ALL

-

BANKS

 command. The SDRAMs must be compatible with this 

format.

READ

Latches the column address and transfers data from the selected sense ampliÞer to the output buffer 
as determined by the column address. During each successive clock, additional data is output without 
additional 

READ

 commands. The amount of data transferred is determined by the burst size. At the end 

of the burst, the page remains open.

REFRESH

Causes a row to be read in both memory banks (JEDEC SDRAM) as determined by the refresh row 
address counter (similar to CBR). The refresh row address counter is internal to the SDRAM device. 
After being read, a row is automatically rewritten into the memory array. Both banks must be in a 
precharged state before executing 

REFRESH

.

WRITE

Latches the column address and transfers data from the data signals to the selected sense ampliÞer 
as determined by the column address. During each successive clock, additional data is transferred to 
the sense ampliÞers from the data signals without additional 

WRITE

 commands. The amount of data 

transferred is determined by the burst size. At the end of the burst, the page remains open.