Motorola MPC8260 User Manual
MOTOROLA
Chapter 10. Memory Controller
10-57
Part III. The Hardware Interface
Figure 10-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)
10.5.1.4 Output Enable (OE) Timing
The timing of the OE is affected only by TRLX. It always asserts and negates on the rising
edge of the external bus clock. OE always asserts on the rising clock edge after CS is
asserted, and therefore its assertion can be delayed (along with the assertion of CS) by
programming TRLX = 1. OE deasserts on the rising clock edge coinciding with or
immediately after CS deassertion.
edge of the external bus clock. OE always asserts on the rising clock edge after CS is
asserted, and therefore its assertion can be delayed (along with the assertion of CS) by
programming TRLX = 1. OE deasserts on the rising clock edge coinciding with or
immediately after CS deassertion.
10.5.1.5 Programmable Wait State ConÞguration
The GPCM supports internal PSDVAL generation. It allows fast accesses to external
memory through an internal bus master or a maximum 17-clock access by programming
ORx[SCY]. The internal PSDVAL generation mode is enabled if ORx[SETA] = 0. If GTA
is asserted externally at least two clock cycles before the wait state counter has expired, the
current memory cycle is terminated. When TRLX = 1, the number of wait states inserted
by the memory controller is deÞned by 2 x SCY or a maximum of 30 wait states.
memory through an internal bus master or a maximum 17-clock access by programming
ORx[SCY]. The internal PSDVAL generation mode is enabled if ORx[SETA] = 0. If GTA
is asserted externally at least two clock cycles before the wait state counter has expired, the
current memory cycle is terminated. When TRLX = 1, the number of wait states inserted
by the memory controller is deÞned by 2 x SCY or a maximum of 30 wait states.
10.5.1.6 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to turn off their data bus drivers on read accesses
should chose some combination of ORx[29Ð30] (TRLX and EHTR). Any access following
a read access to the slower memory bank is delayed by the number of clock cycles speciÞed
by Table 10-31. See Figure 10-50 through Figure 10-53 for timing examples.
should chose some combination of ORx[29Ð30] (TRLX and EHTR). Any access following
a read access to the slower memory bank is delayed by the number of clock cycles speciÞed
by Table 10-31. See Figure 10-50 through Figure 10-53 for timing examples.
Clock
Address
PSDVAL
CS
R/W
WE
OE
Data