Motorola MPC8260 User Manual
MOTOROLA
Chapter 10. Memory Controller
10-79
Part III. The Hardware Interface
Figure 10-66. Wait Mechanism Timing for Internal and External Synchronous
Masters
10.6.4.6 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to turn off their data bus drivers on read accesses
should chose some combination of ORx[EHTR]. Accesses after a read access to the slower
memory bank is delayed by the number of clock cycles speciÞed by Table 10-31. The
information in Section 10.5.1.6, ÒExtended Hold Time on Read Accesses,Ó provides
additional information.
should chose some combination of ORx[EHTR]. Accesses after a read access to the slower
memory bank is delayed by the number of clock cycles speciÞed by Table 10-31. The
information in Section 10.5.1.6, ÒExtended Hold Time on Read Accesses,Ó provides
additional information.
10.6.5 UPM DRAM ConÞguration Example
Consider the following DRAM organization:
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64-bit port size organized as 8 x 8 x 16 Mbits
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Each device has 12 row lines and 9 column lines.
CSx
GPL1
WAEN
Word n
Word n+1
c1
c2
c3
c4
c5
c6
c7
c8
UPWAIT
c9 c10 c11
c12
c13 c14
Word n+2
Wait
Wait
Word n+3
PSDVAL
CLKIN
T1
T2
T3
T4
A
B
C
D