Motorola MPC8260 User Manual
10-100
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
10.8 Handling Devices with Slow or Variable Access
Times
The memory controller provides two ways to interface with slave devices that are very slow
(access time is greater than the maximum allowed by the user programming model) or
cannot guarantee a predeÞned access time (for example some FIFO, hierarchical bus
interface, or dual-port memory devices). These mechanisms are as follows:
(access time is greater than the maximum allowed by the user programming model) or
cannot guarantee a predeÞned access time (for example some FIFO, hierarchical bus
interface, or dual-port memory devices). These mechanisms are as follows:
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The wait mechanismÑUsed only in accesses controlled by the UPM. Setting
MxMR[GPLx4DIS] enables this mechanism.
MxMR[GPLx4DIS] enables this mechanism.
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The external termination (GTA) mechanism is used only in accesses controlled by
the GPCM. ORx[SETA] speciÞes whether the access is terminated internally or
externally.
the GPCM. ORx[SETA] speciÞes whether the access is terminated internally or
externally.
The following examples show how the two mechanisms work.
10.8.1 Hierarchical Bus Interface Example
Assume that the core initiates a local-bus read cycle that addresses main memory connected
to the system bus. The hierarchical bus interface accepts local bus requests and generates a
read cycle on the system bus. The programmer cannot predict when valid data can be
latched by the core because a DMA device may be occupying the system bus.
to the system bus. The hierarchical bus interface accepts local bus requests and generates a
read cycle on the system bus. The programmer cannot predict when valid data can be
latched by the core because a DMA device may be occupying the system bus.
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The wait solution (UPM)ÑThe external module asserts UPWAIT to the memory
controller to indicate that data is not ready. The memory controller synchronized this
signal because the wait signal is asynchronous. As a result of the wait signal being
asserted, the UPM enters a freeze mode at the rising edge of CLKIN upon
encountering the WAEN bit being set in the UPM word. The UPM stays in that state
until UPWAIT is negated. After UPWAIT is negated, the UPM continues executing
from the next entry to the end of the pattern (LAST bit is set).
controller to indicate that data is not ready. The memory controller synchronized this
signal because the wait signal is asynchronous. As a result of the wait signal being
asserted, the UPM enters a freeze mode at the rising edge of CLKIN upon
encountering the WAEN bit being set in the UPM word. The UPM stays in that state
until UPWAIT is negated. After UPWAIT is negated, the UPM continues executing
from the next entry to the end of the pattern (LAST bit is set).
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The external termination solution (GPCM)ÑThe bus interface module asserts GTA
to the memory controller when it can sample data. Note that GTA is also
synchronized.
to the memory controller when it can sample data. Note that GTA is also
synchronized.
10.8.2 Slow Devices Example
Assume that the core initiates a read cycle from a device whose access time exceeds the
maximum allowed by the user programming model.
maximum allowed by the user programming model.
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The wait solution (UPM)ÑThe core generates a read access from the slow device.
The device in turn asserts the wait signal until the data is ready. The core samples
data only after the wait signal is negated.
The device in turn asserts the wait signal until the data is ready. The core samples
data only after the wait signal is negated.
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The external termination solution (GPCM)ÑThe core generates a read access from
the slow device, which must generate the asynchronous GTA when it is ready.
the slow device, which must generate the asynchronous GTA when it is ready.