Motorola MPC8260 User Manual

11-4

MPC8260 PowerQUICC II UserÕs Manual

MOTOROLA

Part III. The Hardware Interface

Figure 11-2. External L2 Cache in Write-Through Mode

11.1.3 ECC/Parity Mode

ECC/parity mode is a subset of write-through mode with some connection changes that
allow the L2 cache to support ECC or Parity. The connection changes are:

The MPC8260Õs DP[0:7] signals are connected to the L2 cacheÕs DP[0:7] signals.

The L2Õs TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction
size.

The L2Õs A[29:31] signals are pulled down.

DBG

TS, TT[0:4], TBST, TSIZ[1Ð3]

A[0Ð31]

CI, GBL, TA, DBB, TEA

CPU_BR, CPU_BG, CPU_DBG

D[0Ð63]

MPC8260

L2BR

L2DBG

TS, TT[0Ð4], TBST, TSIZ[0Ð2]

CI, GBL, TA, DBB, TEA

AACK, ARTRY

CPU_BR,CPU_BG,CPU_DBG

L2_CLAIM

L2_HIT

A[0Ð31]

D[0Ð63]

Memory Controller

SDRAM Main Memory

Latch

MUX

I/O Devices

MPC2605

L2BG

TSIZ[0]

(pull down)

(pull up)