Motorola MPC8260 User Manual
11-8
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part III. The Hardware Interface
bus to the external L2 cache by asserting BG and DBG, respectively. If the external L2
cache asserts ARTRY, it should not assert L2_HIT.
cache asserts ARTRY, it should not assert L2_HIT.
For more information about the timing and behavior of the MPC2605 integrated L2 cache,
refer to the MPC2605 data sheet.
refer to the MPC2605 data sheet.
11.5 Timing Example
Figure 11-4 shows a read access performed by the MPC8260 with an externally controlled
L2 cache. For the Þrst transaction (A0), the MPC8260 grants the bus and asserts TS with
the address and address transfer attributes. In this example, BCR[L2D] = 0, which means
that L2_HIT is valid one clock cycle after the assertion of TS. The MPC8260 samples
L2_HIT when L2D expires. In the second transaction (A1), the access misses in the L2
cache and the memory controller starts the transaction a minimum of three cycles after the
assertion of TS.
L2 cache. For the Þrst transaction (A0), the MPC8260 grants the bus and asserts TS with
the address and address transfer attributes. In this example, BCR[L2D] = 0, which means
that L2_HIT is valid one clock cycle after the assertion of TS. The MPC8260 samples
L2_HIT when L2D expires. In the second transaction (A1), the access misses in the L2
cache and the memory controller starts the transaction a minimum of three cycles after the
assertion of TS.