Motorola MPC8260 User Manual
MOTOROLA
Chapter 13. Communications Processor Module Overview
13-17
Part IV. Communications Processor Module
Only the parameters in the parameter RAM and the microcode RAM option require Þxed
addresses to be used. The BDs, buffer data, and scratchpad RAM can be located in the dual-
port system RAM or in any unused parameter RAM, such as, in the area made available
when a peripheral controller or sub-block is not being used.
addresses to be used. The BDs, buffer data, and scratchpad RAM can be located in the dual-
port system RAM or in any unused parameter RAM, such as, in the area made available
when a peripheral controller or sub-block is not being used.
Microcode can be executed from the Þrst 12 Kbytes. To ensure an uninterrupted instruction
stream (one per cycle), no other agent is allowed to use a RAM bank used by the microcode.
Since the Þrst 12 Kbytes are divided to six 2-Kbyte banks, RAM microcode occupies 2, 4,
6, 8, 10, or 12 Kbytes of RAM, depending on RCCR[ERAM]; see Section 13.3.6, ÒRISC
Controller ConÞguration Register (RCCR).Ó
stream (one per cycle), no other agent is allowed to use a RAM bank used by the microcode.
Since the Þrst 12 Kbytes are divided to six 2-Kbyte banks, RAM microcode occupies 2, 4,
6, 8, 10, or 12 Kbytes of RAM, depending on RCCR[ERAM]; see Section 13.3.6, ÒRISC
Controller ConÞguration Register (RCCR).Ó
13.5.1 Buffer Descriptors (BDs)
The peripheral controllers (FCCs, SCCs, SMCs, MCCs, SPI, and I
2
C) always use BDs for
controlling buffers and their BD formats are all the same, as shown in Table 13-9.
If the IDMA is used in the buffer chaining or auto-buffer mode, the IDMA channel also uses
BDs. They are described in Section 18.3, ÒIDMA Emulation.Ó
BDs. They are described in Section 18.3, ÒIDMA Emulation.Ó
13.5.2 Parameter RAM
The CPM maintains a section of RAM called the parameter RAM, which contains many
parameters for the operation of the FCCs, SCCs, SMCs, SPI, I
parameters for the operation of the FCCs, SCCs, SMCs, SPI, I
2
C, and IDMA channels. An
overview of the parameter RAM structure is shown in Table 13-10.
The exact deÞnition of the parameter RAM is contained in each protocol subsection
describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM
is deÞned differently in some locations from the HDLC-speciÞc parameter RAM.
describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM
is deÞned differently in some locations from the HDLC-speciÞc parameter RAM.
Table 13-9. Buffer Descriptor Format
Address
Descriptor
Offset + 0
Status and control
Offset + 2
Data length
Offset + 4
High-order buffer pointer
Offset + 6
Low-order buffer pointer