Motorola MPC8260 User Manual
14-8
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
Figure 14-4. Enabling Connections to the TSA
14.4 Serial Interface RAM
Each SI has a transmit RAM and a receive RAM, each with four banks of 64 halfword
entries that enable it to control TDM channel routing to all serial devices, including the
MCCs. The SIx RAMs are uninitialized after power-on reset; unwanted results can occur if
the user does not program them before enabling the multiplexed channels.
entries that enable it to control TDM channel routing to all serial devices, including the
MCCs. The SIx RAMs are uninitialized after power-on reset; unwanted results can occur if
the user does not program them before enabling the multiplexed channels.
Each 16-bit SI RAM entry deÞnes the routing of 1Ð8 bits or bytes at a time. In addition to
the routing, up to four strobe pins (logic OR of four strobes in the transmit RAM and four
in receive RAM) can be asserted according to the programming of the RAMs. The four SIx
RAM banks can be conÞgured in many different ways to support various TDM channels.
The user can deÞne the size of each SIx RAM that is related to a certain TDM channel by
programming the starting bank of that TDM. Programming the starting shadow bank
address, described in Section 14.5.3, ÒSIx RAM Shadow Address Registers (SIxRSR),Ó
determines whether this RAM has a shadow for changing SIx RAM entries while the TDM
channel is active. This reduces the number of available SIx RAM entries for that TDM.
the routing, up to four strobe pins (logic OR of four strobes in the transmit RAM and four
in receive RAM) can be asserted according to the programming of the RAMs. The four SIx
RAM banks can be conÞgured in many different ways to support various TDM channels.
The user can deÞne the size of each SIx RAM that is related to a certain TDM channel by
programming the starting bank of that TDM. Programming the starting shadow bank
address, described in Section 14.5.3, ÒSIx RAM Shadow Address Registers (SIxRSR),Ó
determines whether this RAM has a shadow for changing SIx RAM entries while the TDM
channel is active. This reduces the number of available SIx RAM entries for that TDM.
En
En
En
En
SIx RAM
Time-Slot
Assigner
TDM a,b,c,d Enable = 1
TDM a Pins
TDM b Pins
TDM c Pins
TDM d Pins
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
MII1/UTOPIA 16
FC1 = 0
MII2/UTOPIA 8
FC2 = 0
MII3
FC3 = 0
SCC1 pins
SC1 = 0
SCC2 pins
SC2 = 0
SCC3 pins
SC3 = 0
SCC4 pins
SC4 = 0
SMC1 pins
SMC1 = 0
SMC2 pins
SMC2 = 0
MCCx
TDM a channels
TDM b channels
TDM c channels
TDM b channels
TDM c channels
TDM d channels
NMSI Mode
In the CPM mux