Motorola MPC8260 User Manual

 

MOTOROLA

 

  

14-17

 

The serial interface registers are described in the following sections. The MCC
conÞguration registers, which deÞne the TDM mapping of the MCC channels, are
described in Section 27.8, ÒMCC ConÞguration Registers (MCCFx).Ó Note that the
programming of SI registers and SI

 

 RAM must be coherent with the MCCF programming.

 

The SI global mode registers (SI

 

GMR), shown in Figure 14-10, deÞnes the activation state

of the TDM channels for each SI.

 

GMR.

 

There are eight SI mode registers (SI

 

MR), shown in Figure 14-11, one for each TDM

channel (SI

 

AMR, SI

 

BMR, SI

xCMR, and SIxDMR). They are used to deÞne SI operation

modes and allow the user (with SIx RAM) to support any or all of the ISDN channels
independently when in IDL or GCI mode. Any extra serial channel can then be used for
other purposes. 

Bits

0

1

2

3

4

5

6

7

Field

STZD

STZC

STZB

STZA

END

ENC

ENB

ENA

Reset

0000_0000

R/W

R/W

Addr

Figure 14-10. SI Global Mode Registers (SIxGMR)

Table 14-4. SIxGMR Field Descriptions

0Ð3

STZx

Program L1TXDx to zero for TDM a, b, c or d
0 Normal operation
1 L1TXDx = 0 until serial clocks are available, which is useful for GCI activation. See Section 14.7.1, 

ÒSI GCI Activation/Deactivation Procedure.Ó

4Ð7

ENx

Enable TDMx. Note that enabling a TDM is the last step in initialization.
0 TDM channel x is disabled. The SIx RAMs and routing for TDMx are in a state of reset, but all other 

SI functions still operate.

1 All TDMx functions are enabled.