Motorola MPC8260 User Manual
MOTOROLA
Chapter 14. Serial Interface with Time-Slot Assigner
14-23
Part IV. Communications Processor Module
Figure 14-17 shows the effects of changing FE when CE = 0 with no frame sync delay.
Figure 14-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00
14.5.3 SIx RAM Shadow Address Registers (SIxRSR)
The SIx RAM shadow address registers (SIxRSR), shown in Figure 14-18, deÞne the
starting addresses of the shadow section in the SIx RAM for each of the TDM channels.
starting addresses of the shadow section in the SIx RAM for each of the TDM channels.
L1TXD
L1ST
L1SYNC
L1CLK
(Bit-0)
(On Bit-0)
xFSD=00
(FE=1)
CE=0
The L1ST is Driven from Sync.
Data is Driven From Clock High.
Data is Driven From Clock High.
L1TXD
L1ST
L1SYNC
(Bit-0)
(On Bit-0)
(FE=1)
L1ST is Driven from Clock Low.
L1TXD
L1ST
L1SYNC
(Bit-0)
(On Bit-0)
(FE=0)
Both the Data and L1ST from Sync
when Asserted during Clock High.
when Asserted during Clock High.
Rx Sampled Here
L1TXD
L1ST
L1SYNC
(Bit-0)
(On Bit-0)
(FE=0)
Both the Data and L1ST from the Clock
when Asserted during Clock Low.
when Asserted during Clock Low.