Motorola MPC8260 User Manual

lvi

MOTOROLA

Following is a summary and a brief description of the chapters of this manual:

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Part I, ÒOverview,Ó provides a high-level description of the MPC8260, describing 
general operation and listing basic features. 

Ñ Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions 

and features. It roughly follows the structure of this book, summarizing the 
relevant features and providing references for the reader who needs additional 
information.

Ñ Chapter 2, ÒPowerPC Processor Core,Ó provides an overview of the MPC8260 

core, summarizing topics described in further detail in subsequent chapters.

Ñ Chapter 3, ÒMemory Map,Ó presents a table showing where MPC8260 registers 

are mapped in memory. It includes cross references that indicate where the 
registers are described in detail. 

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Part II, ÒConÞguration and Reset,Ó describes start-up behavior of the MPC8260

Ñ Chapter 4, ÒSystem Interface Unit (SIU),Ó describes the system conÞguration 

and protection functions which provide various monitors and timers, and the 60x 
bus conÞguration.

Ñ Chapter 5, ÒReset,Ó describes the behavior of the MPC8260 at reset and start-up.

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Part III, ÒThe Hardware Interface,Ó describes external signals, clocking, memory 
control, and power management of the MPC8260.

Ñ Chapter 6, ÒExternal Signals,Ó shows a functional pinout of the MPC8260 and 

describes the MPC8260 signals. 

Ñ Chapter 7, Ò60x Signals,Ó describes signals on the 60x bus. 

Ñ Chapter 8, ÒThe 60x Bus,Ó describes the operation of the bus used by PowerPC 

processors.

Ñ Chapter 9, ÒClocks and Power Control,Ó describes the clocking architecture of 

the MPC8260.

Ñ Chapter 10, ÒMemory Controller,Ó describes the memory controller, which 

controlling a maximum of eight memory banks shared between a general-
purpose chip-select machine (GPCM) and three user-programmable machines 
(UPMs). 

Ñ Chapter 11, ÒSecondary (L2) Cache Support,Ó provides information about 

implementation and conÞguration of a level-2 cache. 

Ñ Chapter 12, ÒIEEE 1149.1 Test Access Port,Ó describes the dedicated user-

accessible test access port (TAP), which is fully compatible with the IEEE 
1149.1 Standard Test Access Port and Boundary Scan Architecture. 

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Part IV, ÒCommunications Processor Module,Ó describes the conÞguration, 
clocking, and operation of the various communications protocols supported by the 
MPC8260.