Motorola MPC8260 User Manual
19-16
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
Table 19-6 describes RFCRx/TFCRx Þelds.
19.3.3 Handling SCC Interrupts
To allow interrupt handling for SCC-speciÞc events, event, mask, and status registers are
provided within each SCCÕs internal memory map area; see Table 19-7. Because interrupt
events are protocol-dependent, event descriptions are found in the speciÞc protocol
chapters.
provided within each SCCÕs internal memory map area; see Table 19-7. Because interrupt
events are protocol-dependent, event descriptions are found in the speciÞc protocol
chapters.
Table 19-6. RFCRx /TFCRx Field Descriptions
Bits
Name
Description
0Ð1
Ñ
Reserved, should be cleared.
2
GBL
Global
0 Snooping disabled.
1 Snooping enabled.
0 Snooping disabled.
1 Snooping enabled.
3Ð4
BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the
beginning of the next BD.
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the
beginning of the next BD.
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
5
TC2
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6
DTB
Data bus indicator
0 Use 60x bus for SDMA operation
1 Use local bus for SDMA operation
0 Use 60x bus for SDMA operation
1 Use local bus for SDMA operation
7
Ñ
Reserved, should be cleared.
Table 19-7. SCCx Event, Mask, and Status Registers
Register &
IMMR Offset
Description
SCCEx
SCC event register. This 16-bit register reports events recognized by any of the SCCs. When an event
is recognized, the SCC sets its corresponding bit in SCCE, regardless of the corresponding mask bit.
When the corresponding event occurs, an interrupt is signaled to the SIVEC register. Bits are cleared
by writing ones (writing zeros has no effect). SCCE is cleared at reset and can be read at any time.
is recognized, the SCC sets its corresponding bit in SCCE, regardless of the corresponding mask bit.
When the corresponding event occurs, an interrupt is signaled to the SIVEC register. Bits are cleared
by writing ones (writing zeros has no effect). SCCE is cleared at reset and can be read at any time.
SCC mask register. The 16-bit, read/write register allows interrupts to be enabled or disabled using
the CPM for speciÞc events in each SCC channel. An interrupt is generated only if SCC interrupts in
this channel are enabled in the SIU interrupt mask register (SIMR). If an SCCM bit is zero, the CPM
does not proceed with interrupt handling when that event occurs. The SCCM and SCCE bit positions
are identical.
the CPM for speciÞc events in each SCC channel. An interrupt is generated only if SCC interrupts in
this channel are enabled in the SIU interrupt mask register (SIMR). If an SCCM bit is zero, the CPM
does not proceed with interrupt handling when that event occurs. The SCCM and SCCE bit positions
are identical.
SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of RXD.