Motorola MPC8260 User Manual

19-24

MOTOROLA

The DPLL can also be used to invert the data stream of a transfer. This feature is available
in all encodings, including standard NRZ format. Also, when the transmitter is idling, the
DPLL can either force TXD high or continue encoding the data supplied to it. 

The DPLL is used for UART encoding/decoding, which gives the option of selecting the
divide ratio in the UART decoding process (8

´, 16´, or 32´). Typically, 16´ is used.

Note the 1:2 system clock/serial clock ratio does not apply when the DPLL is used to
recover the clock in the 8

´, 16´, or 32´ modes. Synchronization occurs internally after the

DPLL generates the Rx clock. Therefore, even the fastest DPLL clock generation (the 8

´

option) easily meets the required 1:2 ratio clocking limit.

Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC
data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential
Manchester. Figure 19-15 shows the different encoding methods.

NRZI Mark

All zeros

8-bit

NRZI Space

All ones

8-bit

FM0

All ones

8-bit

FM1

All zeros

8-bit

Manchester

101010...10

8-bit

Differential Manchester

All ones

8-bit