Motorola MPC8260 User Manual

20-4

MOTOROLA

receive shift register are transferred to the receive FIFO before proceeding to the receive
buffer. The CPM ßags UART events, including reception errors, in SCCE and the RxBD
status and control Þelds. GSMR_H[RFW] must be set for an 8-bit receive FIFO.

The synchronous UART transmit shift register sends outgoing data on TXDx. Data is then
clocked synchronously with the transmit clock, which can have an internal or external
source. 

For UART mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in
Table 20-1.

0x30

Ñ

DWord Reserved

0x38

Hword Maximum idle characters. When a character is received, the receiver begins 

counting idle characters. If MAX_IDL idle characters are received before the next 
data character, an idle timeout occurs and the buffer is closed, generating a 
maskable interrupt request to the core to receive the data from the buffer. Thus, 
MAX_IDL offers a way to demarcate frames. To disable the feature, clear 
MAX_IDL. The bit length of an idle character is calculated as follows: 1 + data 
length (5Ð9) + 1 (if parity is used) + number of stop bits (1Ð2). For 8 data bits, no 
parity, and 1 stop bit, the character length is 10 bits.

0x3A

IDLC

Hword Temporary idle counter. Holds the current idle count for the idle timeout process. 

IDLC is a down-counter and does not need to be initialized or accessed.

0x3C

Hword Break count register (transmit). Determines the number of break characters the 

transmitter sends. The transmitter sends a break character sequence when a 

STOP

 

TRANSMIT

 command is issued. For 8 data bits, no parity, 1 stop bit, and 1 start bit, 

each break character consists of 10 zero bits.

0x3E

Hword User-initialized,16-bit (moduloÐ2

16

) counters incremented by the CP.

PAREC counts received parity errors. 
FRMEC counts received characters with framing errors. 
NOSEC counts received characters with noise errors. 
BRKEC counts break conditions on the signal. A break condition can last for 
hundreds of bit times, yet BRKEC is incremented only once during that period.

0x40

Hword

0x42

Hword

0x44

Hword

0x46

BRKLN

Hword Last received break length. Holds the length of the last received break character 

sequence measured in character units. For example, if RXDx is low for 20 bit times 
and the deÞned character length is 10 bits, BRKLN = 0x002, indicating that the 
break sequence is at least 2 characters long. BRKLN is accurate to within one 
character length.

0x48

Hword UART address character 1/2. In multidrop mode, the receiver provides automatic 

address recognition for two addresses. In this case, program the lower order bytes 
of UADDR1 and UADDR2 with the two preferred addresses.

0x4A

Hword

0x4C

RTEMP

Hword Temp storage