Motorola MPC8260 User Manual
21-2
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
21.1 SCC HDLC Features
The main features of an SCC in HDLC mode are follows:
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Flexible buffers with multiple buffers per frame
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Separate interrupts for frames and buffers (Rx and Tx)
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Received-frames threshold to reduce interrupt overhead
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Can be used with the SCC DPLL
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Four address comparison registers with mask
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Maintenance of Þve 16-bit error counters
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Flag/abort/idle generation and detection
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Zero insertion/deletion
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16- or 32-bit CRC-CCITT generation and checking
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Detection of nonoctet aligned frames
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Detection of frames that are too long
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Programmable ßags (0Ð15) between successive frames
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Automatic retransmission in case of collision
21.2 SCC HDLC Channel Frame Transmission
The HDLC transmitter is designed to work with little or no core intervention. Once enabled
by the core, a transmitter starts sending ßags or idles as programmed in the HDLC mode
register (PSMR). The HDLC polls the Þrst BD in the TxBD table. When there is a frame to
transmit, the SCC fetches the data (address, control, and information) from the Þrst buffer
and starts sending the frame after inserting the minimum number of ßags speciÞed between
frames. When the end of the current buffer is reached and TxBD[L] (last buffer in frame)
is set, the SCC appends the CRC and closing ßag. In HDLC mode, the lsb of each octet and
the msb of the CRC are sent Þrst. Figure 21-1 shows a typical HDLC frame.
by the core, a transmitter starts sending ßags or idles as programmed in the HDLC mode
register (PSMR). The HDLC polls the Þrst BD in the TxBD table. When there is a frame to
transmit, the SCC fetches the data (address, control, and information) from the Þrst buffer
and starts sending the frame after inserting the minimum number of ßags speciÞed between
frames. When the end of the current buffer is reached and TxBD[L] (last buffer in frame)
is set, the SCC appends the CRC and closing ßag. In HDLC mode, the lsb of each octet and
the msb of the CRC are sent Þrst. Figure 21-1 shows a typical HDLC frame.
Figure 21-1. HDLC Framing Structure
After a closing ßag is sent, the SCC updates the frame status bits of the BD and clears
TxBD[R] (buffer ready). At the end of the current buffer, if TxBD[L] is not set (multiple
buffers per frame), only TxBD[R] is cleared. Before the SCC proceeds to the next TxBD in
the table, an interrupt can be issued if TxBD[I] is set. This interrupt programmability allows
the core to intervene after each buffer, after a speciÞc buffer, or after each frame.
TxBD[R] (buffer ready). At the end of the current buffer, if TxBD[L] is not set (multiple
buffers per frame), only TxBD[R] is cleared. Before the SCC proceeds to the next TxBD in
the table, an interrupt can be issued if TxBD[I] is set. This interrupt programmability allows
the core to intervene after each buffer, after a speciÞc buffer, or after each frame.
The
STOP
TRANSMIT
command can be used to expedite critical data ahead of previously
linked buffers or to support efÞcient error handling. When the SCC receives a
STOP
TRANSMIT
command, it sends idles or ßags instead of the current frame until it receives a
RESTART
TRANSMIT
command. The
GRACEFUL
STOP
TRANSMIT
command can be used to
Opening Flag
Address
Control
Information (Optional)
CRC
Closing Flag
8 bits
16 bits
8 bits
8n bits
16 bits
8 bits