Motorola MPC8260 User Manual
MOTOROLA
Chapter 21. SCC HDLC Mode
21-5
Part IV. Communications Processor Module
Figure 21-2 shows 16- and 8-bit address recognition.
Figure 21-2. HDLC Address Recognition
21.5 Programming the SCC in HDLC Mode
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. The HDLC
controller uses the same buffer and BD data structure as other modes and supports
multibuffer operation and address comparisons. Receive errors are reported through the
RxBD; transmit errors are reported through the TxBD.
controller uses the same buffer and BD data structure as other modes and supports
multibuffer operation and address comparisons. Receive errors are reported through the
RxBD; transmit errors are reported through the TxBD.
21.6 SCC HDLC Commands
The transmit and receive commands are issued to the CP command register (CPCR).
Transmit commands are described in Table 21-2.
Transmit commands are described in Table 21-2.
Table 21-2. Transmit Commands
Command
Description
STOP
TRANSMIT
After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling
the Þrst BD in the TxBD table every 64 Tx clocks, or immediately if TODR[TOD] = 1, and begins sending
data if TxBD[R] is set. If the SCC receives the
the Þrst BD in the TxBD table every 64 Tx clocks, or immediately if TODR[TOD] = 1, and begins sending
data if TxBD[R] is set. If the SCC receives the
STOP
TRANSMIT
command while not transmitting, the
transmitter stops polling the BDs. If the SCC receives the command during transmission, transmission is
aborted after a maximum of 64 additional bits, the Tx FIFO is ßushed, and the current BD pointer TBPTR
is not advanced (no new BD is accessed). The transmitter then sends an abort sequence (0x7F) and
stops polling the BDs.
When not transmitting, the channel sends ßags or idles as programmed in the GSMR.
Note that if PSMR[MFF] = 1, multiple small frames could be ßushed from the Tx FIFO; a
aborted after a maximum of 64 additional bits, the Tx FIFO is ßushed, and the current BD pointer TBPTR
is not advanced (no new BD is accessed). The transmitter then sends an abort sequence (0x7F) and
stops polling the BDs.
When not transmitting, the channel sends ßags or idles as programmed in the GSMR.
Note that if PSMR[MFF] = 1, multiple small frames could be ßushed from the Tx FIFO; a
GRACEFUL
STOP
TRANSMIT
command prevents this.
GRACEFUL
STOP
TRANSMIT
Stops transmission smoothly. Unlike a
STOP
TRANSMIT
command, it stops transmission after the current
frame is Þnished or immediately if no frame is being sent. SCCE[GRA] is set when transmission stops.
HDLC Tx parameters and Tx BDs can then be updated. TBPTR points to the next TxBD. Transmission
begins once TxBD[R] of the next BD is set and a
HDLC Tx parameters and Tx BDs can then be updated. TBPTR points to the next TxBD. Transmission
begins once TxBD[R] of the next BD is set and a
RESTART
TRANSMIT
command is issued.
RESTART
TRANSMIT
Enables frames to be sent on the transmit channel. The HDLC controller expects this command after a
STOP
TRANSMIT
is issued and the channel in its GSMR is disabled, after a
GRACEFUL
STOP
TRANSMIT
command, or after a transmitter error. The transmitter resumes from the current BD.
INIT
TX
PARAMETERS
Resets the Tx parameters in the parameter RAM. Issue only when the transmitter is disabled.
INIT
TX
AND
RX
PARAMETERS
resets both Tx and Rx parameters.
Flag
0x7E
etc.
Flag
0x7E
Address
0x68
Address
0xAA
Control
0x44
etc.
Address
0x55
Control
0x44
16-Bit Address Recognition
8-Bit Address Recognition
0x00FF
HMASK
0xXX55
HADDR1
0xXX55
HADDR2
0xXX55
HADDR3
0xXX55
HADDR4
0xFFFF
HMASK
0xAA68
HADDR1
0xFFFF
HADDR2
0xAA68
HADDR3
0xAA68
HADDR4
Recognizes one 16-bit address (HADDR1) and
the 16-bit broadcast address (HADDR2)
Recognizes a single 8-bit address (HADDR1)