Motorola MPC8260 User Manual
21-12
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
The data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer
Descriptors (BDs).Ó
Descriptors (BDs).Ó
21.11 HDLC Event Register (SCCE)/HDLC Mask
Register (SCCM)
The SCC event register (SCCE) is used as the HDLC event register to report events
recognized by the HDLC channel and to generate interrupts. When an event is recognized,
the SCC sets the corresponding SCCE bit. Interrupts generated through SCCE can be
masked in the SCC mask register (SCCM) which has the same bit format as the SCCE.
Setting an SCCM bit enables the corresponding interrupt; clearing a bit masks it. SCCE bits
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared
before the CP clears the internal interrupt request. Figure 21-7 shows SCCE/SCCM for
HDLC operation.
recognized by the HDLC channel and to generate interrupts. When an event is recognized,
the SCC sets the corresponding SCCE bit. Interrupts generated through SCCE can be
masked in the SCC mask register (SCCM) which has the same bit format as the SCCE.
Setting an SCCM bit enables the corresponding interrupt; clearing a bit masks it. SCCE bits
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared
before the CP clears the internal interrupt request. Figure 21-7 shows SCCE/SCCM for
HDLC operation.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
GLR
GLT
DCC
FLG
IDL
GRA
Ñ
TXE
RXF
BSY
TXB
RXB
Reset
0000_0000_0000_0000
R/W
R/W
Addr
Figure 21-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
Table 21-9. SCCE/SCCM Field Descriptions
Bits
Name
Description
0Ð2
Ñ
Reserved, should be cleared.
3, 4
GLR/
GLT
GLT
Glitch on Rx/Tx. Set when the SCC detects a clock glitch on the receive/transmit clock. See
Section 19.3.7, ÒClock Glitch Detection.Ó
Section 19.3.7, ÒClock Glitch Detection.Ó
5
DCC
DPLL carrier sense changed. Set when the carrier sense status generated by the DPLL changes.
Real-time status can be read in SCCS[CS]. This is not the CD status reported in port C. Valid only
when the DPLL is used.
Real-time status can be read in SCCS[CS]. This is not the CD status reported in port C. Valid only
when the DPLL is used.
6
FLG
Flag status. Set when the SCC stops or starts receiving HDLC ßags. Real-time status can be read in
SCCS[FG].
SCCS[FG].
7
IDL
Idle sequence status changed. Set when HDLC line status changes. Real-time status of the line can
be read in SCCS[ID].
be read in SCCS[ID].
8
GRA
Graceful stop complete. A
GRACEFUL
STOP
TRANSMIT
command completed execution. Set as soon as
the transmitter has sent a frame in progress when the command was issued. Set immediately if no
frame was in progress when the command was issued.
frame was in progress when the command was issued.
9Ð10
Ñ
Reserved, should be cleared.
11
TXE
Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel.