Motorola MPC8260 User Manual
MOTOROLA
Chapter 21. SCC HDLC Mode
21-15
Part IV. Communications Processor Module
21.13.1 SCC HDLC Programming Example #1
The following initialization sequence is for an SCC HDLC channel with an external clock.
SCC2 is used with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver
and transmitter.
SCC2 is used with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver
and transmitter.
1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and
PDIRD[27] and clear PDIRD[28] and PSORD[27,28].
2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26],
PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and
PSORD[26].
PSORD[26].
3. ConÞgure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear
PDIRC[29] and PSORC[29].
4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and
CMXSCR[T2CS].
5. Connect the SCC2 to the NMSI (its own set of pins). clear CMXSCR[SC2].
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and
TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM
and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008.
and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008.
7. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and
TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM
and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008.
and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008.
8. Write 0x04A1_0000 to CPCR to execute the
INIT
RX
AND
TX
PARAMS
command for
SCC2. This command updates RBPTR and TBPTR of the serial channel with the
new values of RBASE and TBASE.
new values of RBASE and TBASE.
9. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.
10. Write MRBLR with the maximum number of bytes per Rx buffer. Choose 256 bytes
(MRBLR = 0x0100) so an entire Rx frame can Þt in one buffer.
11. Write C_MASK with 0x0000F0B8 to comply with 16-bit CCITT-CRC.
12. Write C_PRES with 0x0000FFFF to comply with 16-bit CCITT-CRC.
13. Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for clarity.
14. Write MFLR with 0x0100 so the maximum frame size is 256 bytes.
15. Write RFTHR with 0x0001 to allow interrupts after each frame.
16. Write HMASK with 0x0000 to allow all addresses to be recognized.
17. Clear HADDR1ÐHADDR4 for clarity.
18. Initialize the RxBD. Assume the buffer is at 0x0000_1000 in main memory.
RxBD[Status and Control]= 0xB000, RxBD[Data Length] = 0x0000 (not required),
and RxBD[Buffer Pointer] = 0x0000_1000.
and RxBD[Buffer Pointer] = 0x0000_1000.