Motorola MPC8260 User Manual
22-12
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
22.12 SCC BISYNC Receive BD (RxBD)
The CP uses BDs to report on each buffer received. It closes the buffer, generates a
maskable interrupt, and starts receiving data into the next buffer after any of the following:
maskable interrupt, and starts receiving data into the next buffer after any of the following:
¥
A user-deÞned control character is received.
¥
An error is detected.
¥
A full receive buffer is detected.
¥
The
ENTER
HUNT
MODE
command is issued.
¥
The
CLOSE
RX
BD
command is issued.
Figure 22-6 shows the SCC BISYNC RxBD.
12Ð13 RPM
Receiver parity mode. Selects the type of parity check that the receiver performs. RPM can be
modiÞed on-the-ßy and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled
but can be ignored.
00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is set
modiÞed on-the-ßy and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled
but can be ignored.
00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is set
to ensure an odd number. An even sum indicates a transmission error.
01 Low parity. If the parity bit is not low, a parity error is reported.
10 Even parity. An even number must result from the calculation performed at both ends of the line.
11 High parity. If the parity bit is not high, a parity error is reported.
10 Even parity. An even number must result from the calculation performed at both ends of the line.
11 High parity. If the parity bit is not high, a parity error is reported.
14Ð15 TPM
Transmitter parity mode. Selects the type of parity the transmitter performs and can be modiÞed
on-the-ßy. TPM is ignored unless CRC = 11 (LRC).
00 Odd parity.
01 Force low parity (always send a zero in the parity bit position).
10 Even parity.
11 Force high parity (always send a one in the parity bit position).
on-the-ßy. TPM is ignored unless CRC = 11 (LRC).
00 Odd parity.
01 Force low parity (always send a zero in the parity bit position).
10 Even parity.
11 Force high parity (always send a one in the parity bit position).
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
E
Ñ
W
I
L
F
CM
Ñ
DE
Ñ
NO
PR
CR
OV
CD
Offset + 2
Data Length
Offset + 4
Rx Data Buffer Pointer
Offset + 6
Figure 22-6. SCC BISYNC RxBD
Table 22-11. SCC BISYNC RxBD Status and Control Field Descriptions
Bits
Name
Description
0
E
Empty.
0 The buffer is full or stopped receiving because of an error. The core can read or write any Þelds of this
0 The buffer is full or stopped receiving because of an error. The core can read or write any Þelds of this
RxBD. The CP does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CP controls this BD and buffer. The core should not update this BD.
Table 22-10. PSMR Field Descriptions (Continued)
Bits
Name
Description