Motorola MPC8260 User Manual

22-18

MOTOROLA

After ETX, a BCS is expected; then the buffer should be closed. Hunt mode should be
entered when a line turnaround occurs. ENQ characters are used to stop sending a block
and to designate the end of the block for a receiver, but no CRC is expected. After control
character reception, set SCCM[RCH] to reenable interrupts for each byte of data received.

This BISYNC controller initialization example for SCC2 uses an external clock. The
controller is conÞgured with RTS2, CTS2, and CD2 active. Both the receiver and
transmitter use CLK3.

1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and 

PDIRD[27] and clear PDIRD[28] and PSORD[27,28].

2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], 

PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13], and 
PSORD[26].

3. ConÞgure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear 

PDIRC[29] and PSORC[29]. 

4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and 

CMXSCR[T2CS].

5. Connect the SCC2 to the NMSI (its own set of pins). Clear CMXSCR[SC2].

6. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD, 

write RBASE with 0x0000 and TBASE with 0x0008. 

7. Write 0x04a1_0000 to CPCR to execute 

INIT

 

RX

 

AND

 

TX

 

PARAMETERS

. This updates 

RBPTR and TBPTR to the new values of RBASE and TBASE.

8. Write RFCR and TFCR with 0x10 for normal operation.

9. Write MRBLR with the maximum number of bytes per receive buffer. For this case, 

assume 16 bytes, so MRBLR =  0x0010.

10. Write PRCRC with 0x0000 to comply with CRC16.

11. Write PTCRC with 0x0000 to comply with CRC16.

12. Clear PAREC for clarity.

ETX

0

1

1

ITB

0

1

0

ETB

0

1

1

ENQ

0

0

0

Next entry

0

X

X