Motorola MPC8260 User Manual
MOTOROLA
Chapter 24. SCC Ethernet Mode
24-15
Part IV. Communications Processor Module
24.17 Ethernet Mode Register (PSMR)
In Ethernet mode, the protocol-speciÞc mode register (PSMR), shown in Figure 24-5, is
used as the Ethernet mode register.
used as the Ethernet mode register.
Heartbeat
Some transceivers have a heartbeat (signal-quality error) self-test. To signify a good self-test,
the transceiver indicates a collision to the
the transceiver indicates a collision to the
MPC8260
within 20 clocks after the Ethernet
controller sends a frame. This heartbeat condition does not imply a collision error, but that the
transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the
transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the
MPC8260
does not
detect a heartbeat condition after sending a frame, a heartbeat error occurs; the channel
closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.
closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.
Table 24-5. Reception Errors
Error
Description
Overrun
The Ethernet controller maintains an internal FIFO for receiving data. When it overruns, the channel
writes the received byte over the previously received byte. The previous byte and frame status are lost.
The channel closes the buffer, sets RxBD[OV] and SCCE[RXF], and increments the discarded frame
counter (DISFC). The receiver then enters hunt mode.
writes the received byte over the previously received byte. The previous byte and frame status are lost.
The channel closes the buffer, sets RxBD[OV] and SCCE[RXF], and increments the discarded frame
counter (DISFC). The receiver then enters hunt mode.
Busy
A frame was received and discarded because of a lack of buffers. The channel sets SCCE[BSY] and
increments DISFC. The receiver then enters hunt mode.
increments DISFC. The receiver then enters hunt mode.
Non-Octet
Error
(Dribbling
Bits)
Error
(Dribbling
Bits)
The Ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet
aligned. It checks the CRC of the frame on the last octet boundary. If there is a CRC error, a frame
nonoctet aligned error is reported, SCCE[RXF] is set, and the alignment error counter is incremented. If
there is no CRC error, no error is reported. The receiver then enters hunt mode.
aligned. It checks the CRC of the frame on the last octet boundary. If there is a CRC error, a frame
nonoctet aligned error is reported, SCCE[RXF] is set, and the alignment error counter is incremented. If
there is no CRC error, no error is reported. The receiver then enters hunt mode.
CRC
When a CRC error occurs, the channel closes the buffer, sets SCCE[RXF] and CR in the RxBD, and
increments the CRC error counter (CRCEC). After receiving a frame with a CRC error, the receiver enters
hunt mode. CRC checking cannot be disabled, but CRC errors can be ignored if checking is not required.
increments the CRC error counter (CRCEC). After receiving a frame with a CRC error, the receiver enters
hunt mode. CRC checking cannot be disabled, but CRC errors can be ignored if checking is not required.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
HBC
FC
RSH
IAM
CRC
PRO BRO
SBT
LPB
Ñ
LCW
NIB
FDE
Reset
0000_0000_0000_0000
R/W
R/W
Addr
Figure 24-5. Ethernet Mode Register (PSMR)
Table 24-4. Transmission Errors (Continued)
Error
Description