Motorola MPC8260 User Manual
MOTOROLA
Chapter 24. SCC Ethernet Mode
24-23
Part IV. Communications Processor Module
Note that the SCC status register (SCCS) cannot be used with the Ethernet protocol. The
current state of the RENA and CLSN signals can be found in the parallel I/O ports.
current state of the RENA and CLSN signals can be found in the parallel I/O ports.
24.21 SCC Ethernet Programming Example
The following is an initialization sequence for the SCC2 in Ethernet mode. The CLK3 pin
is used for the Ethernet receiver and CLK4 is used for the transmitter.
is used for the Ethernet receiver and CLK4 is used for the transmitter.
1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and
PDIRD[27] and clear PDIRD[28] and PSORD[27,28].
2. ConÞgure ports C and D pins to enable TENA2 (RTS2), CLSN2 (CTS2) and
RENA2 (CD2). Set PPARD[26], PPARC[12,13] and PDIRD[26] and clear
PDIRC[12,13], PSORC[12,13] and PSORD[26].
PDIRC[12,13], PSORC[12,13] and PSORD[26].
3. ConÞgure port C pins to enable CLK3 and CLK4. Set PPARC[28,29] and clear
PDIRC[28,29] and PSORC[28,29].
4. Connect CLK3 to the SCC2 receiver and CLK4 to the transmitter using the CPM
mux. Program CMXSCR[R2CS] to 0b110 and CMXSCR[T2CS] to 0b111.
5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2].
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and
TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port
RAM and one TxBD following that RxBD, write RBASE with 0x0000 and TBASE
with 0x0008.
RAM and one TxBD following that RxBD, write RBASE with 0x0000 and TBASE
with 0x0008.
7. Write 0x04A1_0000 to the CPCR to execute an
INIT
RX
AND
TX
PARAMETERS
command for this channel.
8. Clear CRCEC, ALEC, and DISFC for clarity.
9. Write PAD with 0x8888 for the PAD value.
10. Write RET_LIM with 0x000F.
11. Write MFLR with 0x05EE to make the maximum frame size 1518 bytes.
12. Write MINFLR with 0x0040 to make the minimum frame size 64 bytes.
13. Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520
bytes.
14. Clear GADDR1ÐGADDR4. The group hash table is not used.
15. Write PADDR1_H with 0x0000, PADDR1_M with 0x0000, and PADDR1_L with
0x0040 to conÞgure the physical address.
16. Clear P_PER. It is not used.
17. Clear IADDR1ÐIADDR4. The individual hash table is not used.
18. Clear TADDR_H, TADDR_M, and TADDR_L for clarity.
19. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main
memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data
Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer].
Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer].