Motorola MPC8260 User Manual

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MOTOROLA
Chapter  1.  Overview  
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Chapter 1  
Overview
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The MPC8260 PowerQUICC IIª is a versatile communications processor that integrates
on one chip a high-performance PowerPCª RISC microprocessor, a very ßexible system
integration unit, and many communications peripheral controllers that can be used in a
variety of applications, particularly in communications and networking systems. 
The core is an embedded variant of the PowerPC MPC603eª microprocessor with 16
Kbytes of instruction cache and 16 Kbytes of data cache and no ßoating-point unit (FPU).
The system interface unit (SIU) consists of a ßexible memory controller that interfaces to
almost any user-deÞned memory system, and many other peripherals making this device a
complete system on a chip. 
The communications processor module (CPM) includes all the peripherals found in the
MPC860, with the addition of three high-performance communication channels that
support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet).
MPC8260 has dedicated hardware that can handle up to 256 full-duplex, time-division-
multiplexed logical channels
This document describes the functional operation of MPC8260, with an emphasis on
peripheral functions. Chapter 2, ÒPowerPC Processor Core,Ó is an overview of the PowerPC
microprocessor core; detailed information about the core can be found in the MPC603e &
EC603e RISC Microprocessors UserÕs Manual 
(order number: MPC603EUM/AD).
1.1  Features
The following is an overview of the MPC8260 feature set:
¥
PowerPC dual-issue integer core
Ñ A core version of the MPC603e microprocessor
Ñ System core microprocessor supporting frequencies of 100Ð200 MHz
Ñ Separate 16-Kbyte data and instruction caches:
РFour-way set associative
РPhysically addressed
РLRU replacement algorithm