Motorola MPC8260 User Manual

26-34

MOTOROLA

Table 26-22 describes SMC C/I channel TxBD Þelds. 

The SMCE generates interrupts and report events recognized by the SMC channel. When
an event is recognized, the SMC sets its corresponding SMCE bit. SMCE bits are cleared
by writing ones; writing zeros has no effect. SMCM has the same bit format as SMCE.
Setting an SMCM bit enables, and clearing an SMCM bit disables, the corresponding
interrupt. Unmasked bits must be cleared before the CP clears the internal interrupt request
to the SIU interrupt controller. 

0

Ready. 
0 Cleared by the CP after transmission to indicate that the BD is available to the core.
1 Set by the core when data associated with this BD is ready for transmission.

1Ð7

Ñ

Reserved, should be cleared.

8Ð13

C/I DATA Command/indication data bits. For C/I channel 0, bits 10Ð13 hold the 4-bit data Þeld (bits 8 and 9 

are always written with zeros). For C/I channel 1, bits 8Ð13 contain the 6-bit data Þeld.

14Ð15 Ñ

Reserved, should be cleared.

Bit

0

1

2

3

4

5

6

7

Field

Ñ

CTXB

CRXB

MTXB

MRXB

Reset

0000_0000

R/W

R/W

Address

0Ð3

Ñ

Reserved, should be cleared.

4

CTXB

C/I channel buffer transmitted. Set when the C/I transmit buffer is now empty.

5

CRXB

C/I channel buffer received. Set when the C/I receive buffer is full.

6

MTXB

Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty.

7

MRXB

Monitor channel buffer received. Set when the monitor receive buffer is full.