Motorola MPC8260 User Manual
27-8
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
27.6 Channel-SpeciÞc HDLC Parameters
Table 27-3. Channel-Specific Parameters for HDLC
Offset
1
1
The offset is relative to dual-port RAM base address + 64*CH_NUM
Name
Width
Description
0x00
TSTATE
Word
Tx internal state. To start a transmitter channel the user must write to TSTATE
0xHH80_0000. HH is the TSTATE high byte described in Section 27.6.1, ÒInternal
Transmitter State (TSTATE).Ó
0xHH80_0000. HH is the TSTATE high byte described in Section 27.6.1, ÒInternal
Transmitter State (TSTATE).Ó
0x04
ZISTATE
Word
Zero-insertion machine state.(User-initialized to 0x10000207 for regular channel, and
0x30000207 for inverted channel)
0x30000207 for inverted channel)
0x08
ZIDATA0
Word
Zero-insertion high word data buffer (User-initialized to 0xFFFFFFFF)
0x0C
ZIDATA1
Word
Zero-insertion low word data buffer (User-initialized to 0xFFFFFFFF)
0x10
TBDFlags
Hword TxDB ßags, used by the CP (read-only for the user)
0x12
TBDCNT
Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x14
TBDPTR
Word
Tx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
CP (read-only for the user)
0x18
INTMSK
Hword ChannelÕs interrupt mask ßag. See Section 27.6.2, ÒInterrupt Mask (INTMSK).Ó
0x1A
CHAMR
Hword Channel mode register. See Section 27.6.3, ÒChannel Mode Register (CHAMR).Ó
0x1C
TCRC
Word
Temp transmit CRC. Temp value of CRC calculation result, used by the CP (read-only for
the user)
the user)
0x20
RSTATE
Word
Rx internal state. To start a receiver channel the user must write to RSTATE
0xHH80_0000. HH is the RSTATE high byte described in Section 27.6.4, ÒInternal
Receiver State (RSTATE).Ó
0xHH80_0000. HH is the RSTATE high byte described in Section 27.6.4, ÒInternal
Receiver State (RSTATE).Ó
0x24
ZDSTATE
Word
Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and
0x20FFFFE0 for inverted channel)
0x20FFFFE0 for inverted channel)
0x28
ZDDATA0
Word
Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
0x2C
ZDDATA1
Word
Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
0x30
RBDFlags Hword RxBD ßags, used by the CP (read-only for the user)
0x32
RBDCNT
Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x34
RBDPTR
Word
Rx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
CP (read-only for the user)
0x38
MFLR
Hword Maximum frame length register. DeÞnes the longest expectable frame for this channel.
(64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded
and the LG ßag is set in the last frameÕs BD. An interrupt request might be generated
(RXF and RXB) depending on the interrupt mask. A frameÕs length is considered to be
everything between ßags, including CRC. No more data is written into the current buffer
when the MFLR violation is detected.
and the LG ßag is set in the last frameÕs BD. An interrupt request might be generated
(RXF and RXB) depending on the interrupt mask. A frameÕs length is considered to be
everything between ßags, including CRC. No more data is written into the current buffer
when the MFLR violation is detected.
0x3A
MAX_CNT Hword Max_length counter, used by the CP (read-only for the user)
0x3C
RCRC
Word
Temp receive CRC, used by the CP (read-only for the user)