Motorola MPC8260 User Manual

1-4

MPC8260 PowerQUICC II UserÕs Manual

MOTOROLA

Part I. Overview

Ñ Two serial management controllers (SMCs), identical to those of the MPC860

Ð Provide management for BRI devices as general-circuit interface (GCI)

controllers in time- division-multiplexed (TDM) channels

Ð Transparent

Ð UART (low-speed operation)

Ñ One serial peripheral interface identical to the MPC860 SPI

Ñ One I

C controller (identical to the MPC860 I

C controller)

Ð Microwire compatible

Ð Multiple-master, single-master, and slave modes

Ñ Up to eight TDM interfaces

Ð Supports two groups of four TDM channels for a total of eight TDMs

Ð 2,048 bytes of SI RAM

Ð Bit or byte resolution

Ð Independent transmit and receive routing, frame synchronization.

Ð Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN

basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general
circuit interface (GCI), and user-deÞned TDM serial interfaces

Ñ Eight independent baud rate generators and 20 input clock pins for supplying

clocks to FCC, SCC, and SMC serial channels

Ñ Four independent 16-bit timers that can be interconnected as two 32-bit timers

1.2 MPC8260Õs Architecture Overview

The MPC8260 has two external buses to accommodate bandwidth requirements from the
high-speed system core and the very fast communications channels. As shown in
Figure 1-1, the MPC8260 has three major functional blocks:

A 64-bit PowerPC core derived from the MPC603e with MMUs and cache

A system interface unit (SIU)

A communications processor module (CPM)