Motorola MPC8260 User Manual

MOTOROLA

Chapter 29. ATM Controller

29-4

Part IV. Communications Processor Module

Available bit rate (ABR)
Ñ Performs ATMF UNI 4.0 ABR ßow control on a per-VC basis
Ñ Automatic forward-RM, backward-RM cells generation
Ñ Automatic feedback rate adaptation
Ñ Support for EFCI (explicit forward congestion indication) and ER (explicit rate)
Ñ RM cell ßoating-point calculations
Ñ Fully managed by CP with no host intervention

Receive address look-up mechanism
Ñ Two modes of address look-up are supported

Ð External CAM
Ð Address compression

OAM (operations and maintenance) cells
Ñ OAM Þltering according to PTI Þeld and reserved VCI Þeld
Ñ Raw cell queues for transmission and reception
Ñ CRC-10 generation/check
Ñ Performance monitoring support

Ð Support up to 64 bidirectional block tests simultaneously
Ð Automatic FMC and BRC cell generation and termination
Ð User transmit cell

0+1

count

Ð User transmit cell

count

Ð PM cells time stamp insertion
Ð Block error detection code (BEDC

0+1

) generation/check

Ð Total receive cell

0+1

count

Ð Total receive cell

count

Ñ Specifying channel code for F5 OAM cells

ATM layer statistic gathering on a per PHY basis.
Ñ UTOPIA receiver error cells count (Rx parity error or short/long cells error)
Ñ Misinserted cell count
Ñ CRC-10 error cells count (ABR ßow only)

Memory management
Ñ RxBD table per VC with option of global free buffer pool for AAL5
Ñ TxBD table per VC

29.2 ATM Controller Overview

The following sections provide an overview of the transmitter and receiver portions of the
ATM controller.