Motorola MPC8260 User Manual
MOTOROLA
Chapter 29. ATM Controller
29-91
Part IV. Communications Processor Module
29.15 SRTS Generation and Clock Recovery Using
External Logic
The MPC8260 supports SRTS generation using external logic. If SRTS generation is
enabled (TCT[SRT] = 1), the MPC8260 reads SRTS[0Ð3] from the external SRTS logic and
inserts it into 4 cells whose SN Þelds equal 1, 3, 5, and 7, as shown in Figure 29-64.
enabled (TCT[SRT] = 1), the MPC8260 reads SRTS[0Ð3] from the external SRTS logic and
inserts it into 4 cells whose SN Þelds equal 1, 3, 5, and 7, as shown in Figure 29-64.
Figure 29-64. AAL1 SRTS Generation Using External Logic
For every eight cells, the external SRTS logic should supply a valid SRTS code. The CP
reads the SRTS code from the bus selected in TCT[BIB] using a DMA read cycle of 1-byte
data size. Each AAL1 channel can be programmed to select one of 16 addresses available
for reading the SRTS result. The SRTS code should be placed on the least-signiÞcant nibble
of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is synchronized with the
sequence count cycleÑSRTS[0] is inserted into the cell with SN = 7; SRTS[3] is inserted
into the cell with SN = 1. For every eighth AAL1 SAR PDU, the SRTS logic samples a new
SRTS and stores it internally. The SRTS is a sample of a 4-bit counter with a 2.43-MHz
reference clock (for E1/T1) synchronized with the network clock.
reads the SRTS code from the bus selected in TCT[BIB] using a DMA read cycle of 1-byte
data size. Each AAL1 channel can be programmed to select one of 16 addresses available
for reading the SRTS result. The SRTS code should be placed on the least-signiÞcant nibble
of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is synchronized with the
sequence count cycleÑSRTS[0] is inserted into the cell with SN = 7; SRTS[3] is inserted
into the cell with SN = 1. For every eighth AAL1 SAR PDU, the SRTS logic samples a new
SRTS and stores it internally. The SRTS is a sample of a 4-bit counter with a 2.43-MHz
reference clock (for E1/T1) synchronized with the network clock.
The MPC8260 supports clock recovery using an external SRTS PLL. If SRTS recovery is
enabled (RCT[SRT]=1), the MPC8260 tracks the SRTS from four incoming cells whose
SN Þeld equals 1, 3, 5, and 7 and writes the result to external SRTS logic, as shown in
Figure 29-65.
enabled (RCT[SRT]=1), the MPC8260 tracks the SRTS from four incoming cells whose
SN Þeld equals 1, 3, 5, and 7 and writes the result to external SRTS logic, as shown in
Figure 29-65.
p = 4 bit counter
1/64
155.52 MHz
2.43 MHz (E1/T1)
Latch
fs
Counter
divided by N
(N=3008 bits = 8 SAR PDU)
SRTS
External SRTS Logic
SN=1
SN=3
SN=5
SN=7
DMA reads new SRTS code