Motorola MPC8260 User Manual

30-4

MOTOROLA

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Multibuffer data structure

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Supports 48-bit addresses in three modes
Ñ Physical. One 48-bit address recognized or 64-bin hash table for physical 

addresses

Ñ Logical. 64-bin group address hash table plus broadcast address checking
Ñ Promiscuous. Receives all frames regardless of address (a CAM can be used for 

address Þltering)

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External CAM support on system bus interfaces

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Special RMON counters for monitoring network statistics

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Up to eight parallel I/O pins can be sampled and appended to any frame

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Transmitter network management and diagnostics
Ñ Lost carrier sense
Ñ Underrun
Ñ Number of collisions exceeded the maximum allowed
Ñ Number of retries per frame
Ñ Deferred frame indication
Ñ Late collision

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Receiver network management and diagnostics
Ñ CRC error indication
Ñ Nonoctet alignment error
Ñ Frame too short
Ñ Frame too long
Ñ Overrun
Ñ Busy (out of buffers)

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Error counters
Ñ Discarded frames (out of buffers or overrun occurred)
Ñ CRC errors
Ñ Alignment errors

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Internal and external loopback mode

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Supports Fast Ethernet in duplex mode

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Supports pause ßow control frames

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Support of out-of-sequence transmit queue (for ßow-control frames)

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External buffer descriptors (BDs) 

Figure 30-3 shows the basic components of the media-independent interface (MII) and the
signals required to make the Fast Ethernet connection between the MPC8260 and a PHY.