Motorola MPC8260 User Manual
30-12
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
30.9 Programming Model
The core conÞgures an FCC to operate as an Ethernet controller using GFMR[MODE]. The
receive errors (collision, overrun, nonoctet-aligned frame, short frame, frame too long, and
CRC error) are reported through the RxBD. The transmit errors (underrun, heartbeat, late
collision, retransmission limit, and carrier sense lost) are reported through the TxBD.
receive errors (collision, overrun, nonoctet-aligned frame, short frame, frame too long, and
CRC error) are reported through the RxBD. The transmit errors (underrun, heartbeat, late
collision, retransmission limit, and carrier sense lost) are reported through the TxBD.
Synchronization Registers (FDSRx),Ó with FDSR[SYN2] = 0xD5 and FDSR[SYN1] =
0x55.
0x55.
30.10 Ethernet Command Set
The transmit and receive commands are issued to the CPCR; see Section 13.4, ÒCommand
Set.Ó
Set.Ó
NOTE
Before resetting the CPM, conÞgure TX_EN (RTS) to be an
input.
input.
0xE8
P128C
Word
(RMON mode only) The total number of packets (including bad packets) received
that were between 128 and 255 octets long inclusive (excluding framing bits but
including FCS octets).
that were between 128 and 255 octets long inclusive (excluding framing bits but
including FCS octets).
0xEC
P256C
Word
(RMON mode only) The total number of packets (including bad packets) received
that were between 256 and 511 octets long inclusive (excluding framing bits but
including FCS octets).
that were between 256 and 511 octets long inclusive (excluding framing bits but
including FCS octets).
0xF0
P512C
Word
(RMON mode only) The total number of packets (including bad packets) received
that were between 512 and 1023 octets long inclusive (excluding framing bits but
including FCS octets).
that were between 512 and 1023 octets long inclusive (excluding framing bits but
including FCS octets).
0xF4
Word
(RMON mode only) The total number of packets (including bad packets) received
that were between 1024 and 1518 octets long inclusive (excluding framing bits but
including FCS octets).
that were between 1024 and 1518 octets long inclusive (excluding framing bits but
including FCS octets).
0xF8
CAM_BUF
Word
Internal buffer for CAM result
0xFC
Ñ
Word
Reserved, should be cleared.
1
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 13.5.2, ÒParameter RAM.Ó
2
32-bit (modulo 232) counters maintained by the CP; cleared by the user while the channel is disabled.
Table 30-3. Transmit Commands
Command
Description
STOP
TRANSMIT
When used with the Ethernet controller, this command violates a speciÞc behavior of an Ethernet/IEEE
802.3 station. It should not be used.
802.3 station. It should not be used.
Table 30-2. Ethernet-Specific Parameter RAM (Continued)
Offset
1
Name
Width
Description