Motorola MPC8260 User Manual
31-2
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
31.1 Key Features
Key features of the HDLC include the following:
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Flexible data buffers with multiple buffers per frame
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Separate interrupts for frames and buffers (receive and transmit)
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Received frames threshold to reduce interrupt overhead
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Four address comparison registers with masks
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Maintenance of four 16-bit error counters
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Flag/abort/idle generation and detection
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Zero insertion/deletion
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16- or 32-bit CRC-CCITT generation/checking
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Detection of nonoctet-aligned frames
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Detection of frames that are too long
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Programmable ßags (0Ð15) between successive frames
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External BD table
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Up to T3 rate
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Support of time stamp mode for Rx frames
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Support of nibble mode HDLC (4 bits per clocks)
31.2 HDLC Channel Frame Transmission Processing
The HDLC transmitter is designed to work with almost no core intervention. When the core
enables a transmitter, it starts sending ßags or idles as programmed in the HDLC mode
register (FPSMR). The HDLC controller polls the Þrst BD in the transmit channel BD table.
When there is a frame to transmit, the HDLC controller fetches the data (address, control,
and information) from the Þrst buffer and begins sending the frame after Þrst inserting the
user-speciÞed minimum number of ßags between frames. When the end of the current
buffer is reached and TxBD[L] (last buffer in frame) is set, the FCC appends the CRC (if
selected) and closing ßag. In HDLC, the lsb of each octet and the msb of the CRC are sent
Þrst. Figure 31-1 shows a typical HDLC frame.
enables a transmitter, it starts sending ßags or idles as programmed in the HDLC mode
register (FPSMR). The HDLC controller polls the Þrst BD in the transmit channel BD table.
When there is a frame to transmit, the HDLC controller fetches the data (address, control,
and information) from the Þrst buffer and begins sending the frame after Þrst inserting the
user-speciÞed minimum number of ßags between frames. When the end of the current
buffer is reached and TxBD[L] (last buffer in frame) is set, the FCC appends the CRC (if
selected) and closing ßag. In HDLC, the lsb of each octet and the msb of the CRC are sent
Þrst. Figure 31-1 shows a typical HDLC frame.
Figure 31-1. HDLC Framing Structure
After the closing ßag is sent, the HDLC controller writes the frame status bits into the BD
and clears the R bit. When the end of the current BD is reached and the L (last) bit is not
set (working in multibuffer mode), only the R bit is cleared. In either mode, an interrupt can
be issued if the I bit in the TxBD is set. The HDLC controller then proceeds to the next
TxBD in the table. In this way, the core can be interrupted after each buffer, after a speciÞc
buffer, after each frame, or after a number of frames.
and clears the R bit. When the end of the current BD is reached and the L (last) bit is not
set (working in multibuffer mode), only the R bit is cleared. In either mode, an interrupt can
be issued if the I bit in the TxBD is set. The HDLC controller then proceeds to the next
TxBD in the table. In this way, the core can be interrupted after each buffer, after a speciÞc
buffer, after each frame, or after a number of frames.
Opening Flag
Address
Control
Information (Optional)
CRC
Closing Flag
8 Bits
16 Bits
8 Bits
8n Bits
16 Bits
8 Bits