Motorola MPC8260 User Manual

34-2

MOTOROLA

The I

2

C receiver and transmitter are double-buffered, which corresponds to an effective

two-character FIFO latency. In normal operation, the transmitter shifts the msb (bit 0) out
Þrst. When the I

2

C is not enabled in the I

2

C mode register (I2MOD[EN] = 0), it consumes

little power.

The following is a list of the I

2

C controllerÕs main features:

¥

Two-signal interface (SDA and SCL)

¥

Support for master and slave I

2

C operation 

¥

Multiple-master environment support

¥

Continuous transfer mode for automatic scanning of a peripheral

¥

Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%), 
assuming a 100-MHz system clock.

¥

Independent, programmable baud-rate generator

¥

Supports 7-bit I

2

C addressing

¥

Open-drain output signals allow multiple master conÞguration

¥

Local loopback capability for testing

The I

2

C controller can be conÞgured as a master or slave for the serial channel. As a master,

the controllerÕs BRG provides the transfer clock. The I

2

C BRG takes its input from the BRG

clock (BRGCLK), which is generated from the CPM clock; see Section 9.8, ÒSystem Clock
Control Register (SCCR).Ó 

SDA and SCL are bidirectional signals connected to a positive supply voltage through an
external pull-up resistor. When the bus is free, both signals are pulled high. The general I

2

C

master/slave conÞguration is shown in Figure 34-2.

VDD

VDD

Master

Slave

(EEPROM, for example)

SCL

SCL

SDA

SDA