Motorola MPC8260 User Manual
35-2
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
35.2 Port Registers
Each port has four memory-mapped, read/write, 32-bit control registers.
35.2.1 Port Open-Drain Registers (PODRAÐPODRD)
The port open-drain register (PODR), shown in Figure 35-1, indicates a normal or wired-
OR conÞguration of the port pins.
OR conÞguration of the port pins.
35.2.2 Port Data Registers (PDATAÐPDATD)
A read of a port data register (PDATx), shown in Figure 35-2, returns the data at the pin,
independent of whether the pin is deÞned as an input or output. This allows detection of
output conßicts at the pin by comparing the written data with the data on the pin.
independent of whether the pin is deÞned as an input or output. This allows detection of
output conßicts at the pin by comparing the written data with the data on the pin.
A write to the PDATx is latched and if the equivalent PDIR bit is conÞgured as an output,
the value latched for that bit is driven onto its respective pin. PDATx can be read or written
at any time and is not initialized.
the value latched for that bit is driven onto its respective pin. PDATx can be read or written
at any time and is not initialized.
If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port
data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin
is conÞgured as an output, the output latch data is gated onto the port pin. In this case, when
PDATx is read, the port pin itself is read. If a port pin is conÞgured as an input, data written
data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin
is conÞgured as an output, the output latch data is gated onto the port pin. In this case, when
PDATx is read, the port pin itself is read. If a port pin is conÞgured as an input, data written
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
OD0
1
OD1
1
OD2
1
OD3
1
OD4
OD5
OD6
OD7
OD8
OD9 OD10 OD11 OD12 OD13 OD14 OD15
Reset
0000_0000_0000_0000
R/W
R/W
Addr
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
OD16 OD17 OD18 OD19 OD20 OD21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset
0000_0000_0000_0000
R/W
R/W
Addr
0x10D0E (PODRA), 0x10D2E (PODRB), 0x10D4E (PODRC), 0x10D6E (PODRD)
1
These bits are valid for PODRA and PODRC only
Figure 35-1. Port Open-Drain Registers (PODRAÐPODRD)
Table 35-1. PODRx Field Descriptions
Bits
Name
Description
0Ð31
ODx
Open-drain conÞguration. Determines whether the corresponding pin is actively driven as an output or is
an open-drain driver. Note that bits OD0ÐOD3 are valid for PODRA and PODRC only.
0 The I/O pin is actively driven as an output.
1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is three-stated.
an open-drain driver. Note that bits OD0ÐOD3 are valid for PODRA and PODRC only.
0 The I/O pin is actively driven as an output.
1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is three-stated.