Intel 8XC196MC User Manual
5-55
STANDARD AND PTS INTERRUPTS
5.6.6.4
Asynchronous SIO Receive Mode Example
In asynchronous serial I/O (ASIO) receive mode, an EPA channel is set up to capture the falling
edge when the data start bit toggles on a port pin that is configured to function as the Receive Data
signal (RXD). When the capture occurs, the EPA generates a conventional interrupt which starts
the asynchronous receive process. This conventional interrupt service routine would be the same
as the end-of-PTS interrupt service routine. It changes the EPA channel to the compare mode and
sets the time of the next compare to 1.5 bit times and enables the PTS. At exactly 1.5 bit times
from the beginning of the start bit, the first PTS cycle samples the input data on RXD and shifts
it into the DATA register (Figure 5-27). If majority sampling is enabled, an additional sample oc-
curs. If the two samples differ, a third sample occurs to determine which of the first two samples
is correct. The SAMPTIME register (Figure 5-19 on page 5-38) controls the time between sam-
ples. Majority sampling causes a substantial increase in PTS cycle execution time (Table 5-4 on
page 5-12).
edge when the data start bit toggles on a port pin that is configured to function as the Receive Data
signal (RXD). When the capture occurs, the EPA generates a conventional interrupt which starts
the asynchronous receive process. This conventional interrupt service routine would be the same
as the end-of-PTS interrupt service routine. It changes the EPA channel to the compare mode and
sets the time of the next compare to 1.5 bit times and enables the PTS. At exactly 1.5 bit times
from the beginning of the start bit, the first PTS cycle samples the input data on RXD and shifts
it into the DATA register (Figure 5-27). If majority sampling is enabled, an additional sample oc-
curs. If the two samples differ, a third sample occurs to determine which of the first two samples
is correct. The SAMPTIME register (Figure 5-19 on page 5-38) controls the time between sam-
ples. Majority sampling causes a substantial increase in PTS cycle execution time (Table 5-4 on
page 5-12).
Figure 5-27. Asynchronous SIO Receive Timing
The first PTS cycle must be started manually.
•
Initialize the RXD port pin and the SCK signal to the system-required logic level before
starting a reception.
starting a reception.
•
Add the contents of the timer register to the Baud_value (Figure 5-19 on page 5-38) and
store the result into the EPA time register. This sets up the timing for the first interrupt and
causes the first interrupt to occur at the proper baud rate.
store the result into the EPA time register. This sets up the timing for the first interrupt and
causes the first interrupt to occur at the proper baud rate.
The following example uses EPA0 to capture the start bit and P2.0 to receive the data (RXD). It
sets up an asynchronous serial I/O PTS routine that receives 16 bytes each with eight data bits and
a parity bit. This example uses several user-defined registers. R_COUNT defines the number of
bytes to receive and RXDDONE is a flag that is set when all bytes are received.
sets up an asynchronous serial I/O PTS routine that receives 16 bytes each with eight data bits and
a parity bit. This example uses several user-defined registers. R_COUNT defines the number of
bytes to receive and RXDDONE is a flag that is set when all bytes are received.
1.
Disable the interrupts and the PTS.
— Use the DI instruction to disable all standard interrupts and the DPTS instruction to
disable the PTS.
A3118-01
Interrupts
Stop
Start
LSB
RXD
(Port pin)
(Port pin)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Parity
MSB
1.5 Bit Times
Optional
Parity Bit
Parity Bit
End-of-PTS
Conventional
Interrupt
10 PTS Serviced Interrupts
Conventional
Interrupt
Interrupt