Intel 8XC196MC User Manual
9-5
WAVEFORM GENERATOR
9.3.2
Phase Driver Channels
The phase driver channels determine the duty cycle of the outputs. You specify the duty cycle by
writing a value to each phase’s compare register (WG_COMPx). In all operating modes, the out-
puts are initially asserted, and they remain asserted until the counter value (WG_COUNTER)
matches the phase’s compare register (WG_COMPx) value. At this point, the outputs are deas-
serted and remain deasserted until another event occurs. The event that causes the outputs to be
asserted again depends on the operating mode. (See “Operating Modes” on page 9-7.)
writing a value to each phase’s compare register (WG_COMPx). In all operating modes, the out-
puts are initially asserted, and they remain asserted until the counter value (WG_COUNTER)
matches the phase’s compare register (WG_COMPx) value. At this point, the outputs are deas-
serted and remain deasserted until another event occurs. The event that causes the outputs to be
asserted again depends on the operating mode. (See “Operating Modes” on page 9-7.)
The dead-time generator circuitry (Figure 9-2) prevents an output and its complement from being
asserted at the same time. It uses two internal signals, WFG and DT, to generate the nonoverlap-
ping outputs. The edge-detection circuitry generates the WFG signal, while a 10-bit dead-time
counter generates the DT signal. When a valid edge is detected, the dead-time counter is loaded
with the 10-bit dead-time value from the control register and DT is driven low. The counter dec-
rements once every state time until it reaches zero, at which point the counter stops and DT is
driven high. The WFG signal is ANDed with DT to produce the WG_EVEN signal; the WFG#
signal is ANDed with DT to produce the WG_ODD signal. The waveform generator’s outputs
can be connected to the WG_EVEN and WG_ODD signals. (See “Configuring the Outputs” on
page 9-12.)
asserted at the same time. It uses two internal signals, WFG and DT, to generate the nonoverlap-
ping outputs. The edge-detection circuitry generates the WFG signal, while a 10-bit dead-time
counter generates the DT signal. When a valid edge is detected, the dead-time counter is loaded
with the 10-bit dead-time value from the control register and DT is driven low. The counter dec-
rements once every state time until it reaches zero, at which point the counter stops and DT is
driven high. The WFG signal is ANDed with DT to produce the WG_EVEN signal; the WFG#
signal is ANDed with DT to produce the WG_ODD signal. The waveform generator’s outputs
can be connected to the WG_EVEN and WG_ODD signals. (See “Configuring the Outputs” on
page 9-12.)
Figure 9-2. Dead-time Generator Circuitry
9.3.3
Control and Protection Circuitry
The control circuitry contains the control (WG_CONTROL) and output (WG_OUTPUT) regis-
ters. The control register enables or disables the counter, specifies the count direction, controls
the operating mode, and specifies the dead time for all three phases. The output register config-
ures the pins, specifies the output polarity (active high or active low), and controls whether the
outputs are updated immediately or are synchronized with an event.
ters. The control register enables or disables the counter, specifies the count direction, controls
the operating mode, and specifies the dead time for all three phases. The output register config-
ures the pins, specifies the output polarity (active high or active low), and controls whether the
outputs are updated immediately or are synchronized with an event.
A2640-01
P6.1 / WG1
P6.0 / WG1#
Output Disable
From
Protection Circuit
10-Bit Counter
Start/ CNT=0
Load
Start/ CNT=0
Load
DT
From
Phase
Comparator
10-Bit Value
Transition
Detector
Trigger
Both
Edges
WG_CONTROL
Bits 0 – 9
WG_EVEN
Output
Circuitry
WG_ODD
WFG
WFG#
To Other
Channels