Intel 8XC196MC User Manual
8XC196MC, MD, MH USER’S MANUAL
12-4
Once the A/D converter receives the command to start a conversion, a delay time elapses before
sampling begins. (EPA-initiated conversions begin after the capture/compare event. Immediate
conversions, those initiated directly by a write to AD_COMMAND, begin within three state
times after the instruction is completed.) During this sample delay, the hardware clears the suc-
cessive approximation register and selects the designated multiplexer channel. After the sample
delay, the device connects the multiplexer output to the sample capacitor for the specified sample
time. After this sample window closes, it disconnects the multiplexer output from the sample ca-
pacitor so that changes on the input pin will not alter the stored charge while the conversion is in
progress. The device then zeros the comparator and begins the conversion.
sampling begins. (EPA-initiated conversions begin after the capture/compare event. Immediate
conversions, those initiated directly by a write to AD_COMMAND, begin within three state
times after the instruction is completed.) During this sample delay, the hardware clears the suc-
cessive approximation register and selects the designated multiplexer channel. After the sample
delay, the device connects the multiplexer output to the sample capacitor for the specified sample
time. After this sample window closes, it disconnects the multiplexer output from the sample ca-
pacitor so that changes on the input pin will not alter the stored charge while the conversion is in
progress. The device then zeros the comparator and begins the conversion.
The A/D converter uses a successive approximation algorithm to perform the analog-to-digital
conversion. The converter hardware consists of a 256-resistor ladder, a comparator, coupling ca-
pacitors, and a 10-bit successive approximation register (SAR) with logic that guides the process.
The resistive ladder provides 20 mV steps (V
conversion. The converter hardware consists of a 256-resistor ladder, a comparator, coupling ca-
pacitors, and a 10-bit successive approximation register (SAR) with logic that guides the process.
The resistive ladder provides 20 mV steps (V
REF
= 5.12 volts), while capacitive coupling creates
5 mV steps within the 20 mV ladder voltages. Therefore, 1024 internal reference voltage levels
are available for comparison against the analog input to generate a 10-bit conversion result. In 8-
bit conversion mode, only the resistive ladder is used, providing 256 internal reference voltage
levels.
are available for comparison against the analog input to generate a 10-bit conversion result. In 8-
bit conversion mode, only the resistive ladder is used, providing 256 internal reference voltage
levels.
The successive approximation conversion compares a sequence of reference voltages to the ana-
log input, performing a binary search for the reference voltage that most closely matches the in-
put. The ½ full scale reference voltage is the first tested. This corresponds to a 10-bit result where
the most-significant bit is zero and all other bits are ones (0111111111B). If the analog input was
less than the test voltage, bit 10 of the SAR is left at zero, and a new test voltage of ¼ full scale
(0011111111B) is tried. If the analog input was greater than the test voltage, bit 9 of SAR is set.
Bit 8 is then cleared for the next test (0101111111B). This binary search continues until 10 (or 8)
tests have occurred, at which time the valid conversion result resides in the AD_RESULT register
where it can be read by software. The result is equal to the ratio of the input voltage divided by
the analog supply voltage. If the ratio is 1.00, the result will be all ones.
log input, performing a binary search for the reference voltage that most closely matches the in-
put. The ½ full scale reference voltage is the first tested. This corresponds to a 10-bit result where
the most-significant bit is zero and all other bits are ones (0111111111B). If the analog input was
less than the test voltage, bit 10 of the SAR is left at zero, and a new test voltage of ¼ full scale
(0011111111B) is tried. If the analog input was greater than the test voltage, bit 9 of SAR is set.
Bit 8 is then cleared for the next test (0101111111B). This binary search continues until 10 (or 8)
tests have occurred, at which time the valid conversion result resides in the AD_RESULT register
where it can be read by software. The result is equal to the ratio of the input voltage divided by
the analog supply voltage. If the ratio is 1.00, the result will be all ones.
12.4 PROGRAMMING THE A/D CONVERTER
The following A/D converter parameters are programmable:
•
conversion input — input channel
•
zero-offset adjustment — no adjustment, plus 2.5 mV, minus 2.5 mV, or minus 5.0 mV
•
conversion times — sample window time and conversion time for each bit
•
operating mode — 8- or 10-bit conversion or 8-bit high or low threshold detection
•
conversion trigger — immediate or EPA starts
This section describes the A/D converter’s registers and explains how to program them.