Intel 8XC196MC User Manual
8XC196MC, MD, MH USER’S MANUAL
A-6
Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands.
Table A-5. Operand Variables
Variable
Description
aa
A 2-bit field within an opcode that selects the basic addressing mode used. This field is present
only in those opcodes that allow addressing mode options. The field is encoded as follows:
only in those opcodes that allow addressing mode options. The field is encoded as follows:
00 register-direct
01 immediate
10 indirect
11 indexed
baop
A byte operand that is addressed by any addressing mode.
bbb
A 3-bit field within an opcode that selects a specific bit within a register.
bitno
A 3-bit field within an opcode that selects one of the eight bits in a byte.
breg
A byte register in the internal register file. When it could be unclear whether this variable refers
to a source or a destination register, it is prefixed with an
to a source or a destination register, it is prefixed with an
S
or a
D
. The value must be in the
range of 00–FFH.
cadd
An address in the program code.
Dbreg
†
A byte register in the lower register file that serves as the destination of the instruction
operation.
operation.
disp
Displacement. The distance between the end of an instruction and the target label.
Dlreg
†
A 32-bit register in the lower register file that serves as the destination of the instruction
operation. Must be aligned on an address that is evenly divisible by 4. The value must be in the
range of 00–FCH.
operation. Must be aligned on an address that is evenly divisible by 4. The value must be in the
range of 00–FCH.
Dwreg
†
A word register in the lower register file that serves as the destination of the instruction
operation. Must be aligned on an address that is evenly divisible by 2. The value must be in the
range of 00–FEH.
operation. Must be aligned on an address that is evenly divisible by 2. The value must be in the
range of 00–FEH.
lreg
A 32-bit register in the lower register file. Must be aligned on an address that is evenly divisible
by 4. The value must be in the range of 00–FCH.
by 4. The value must be in the range of 00–FCH.
preg
A pointer register. Must be aligned on an address that is evenly divisible by 4. The value must
be in the range of 00–FCH.
be in the range of 00–FCH.
Sbreg
†
A byte register in the lower register file that serves as the source of the instruction operation.
Slreg
†
A 32-bit register in the lower register file that serves as the source of the instruction operation.
Must be aligned on an address that is evenly divisible by 4. The value must be in the range of
00–FCH.
Must be aligned on an address that is evenly divisible by 4. The value must be in the range of
00–FCH.
Swreg
†
A word register in the lower register file that serves as the source of the instruction operation.
Must be aligned on an address that is evenly divisible by 2. The value must be in the range of
00–FEH.
Must be aligned on an address that is evenly divisible by 2. The value must be in the range of
00–FEH.
waop
A word operand that is addressed by any addressing mode.
w2_reg
A double-word register in the lower register file. Must be aligned on an address that is evenly
divisible by 4. The value must be in the range of 00–FCH. Although
divisible by 4. The value must be in the range of 00–FCH. Although
w2_reg
is similar to
lreg
,
there is a distinction:
w2_reg
consists of two halves, each containing a 16-bit address;
lreg
is
indivisible and contains a 32-bit number.
wreg
A word register in the lower register file. When it could be unclear whether this variable refers
to a source or a destination register, it is prefixed with an
to a source or a destination register, it is prefixed with an
S
or a
D
. Must be aligned on an
address that is evenly divisible by 2. The value must be in the range of 00–FEH.
xxx
The three high-order bits of displacement.
†
The
D
or
S
prefix is used only when it could be unclear whether a variable refers to a destination or a
source register.