Intel 8XC196MC User Manual
8XC196MC, MD, MH USER’S MANUAL
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2.3.4
Memory Interface Unit
The RALU communicates with all memory, except the register file and peripheral SFRs, through
the memory controller. (It communicates with the upper register file through the memory control-
ler except when windowing is used; see Chapter 4, “Memory Partitions.”) The memory controller
contains the prefetch queue, the slave program counter (slave PC), address and data registers, and
the bus controller.
the memory controller. (It communicates with the upper register file through the memory control-
ler except when windowing is used; see Chapter 4, “Memory Partitions.”) The memory controller
contains the prefetch queue, the slave program counter (slave PC), address and data registers, and
the bus controller.
The bus controller drives the memory bus, which consists of an internal memory bus and the ex-
ternal address/data bus. The bus controller receives memory-access requests from either the
RALU or the prefetch queue; queue requests always have priority. This queue is transparent to
the RALU and your software.
ternal address/data bus. The bus controller receives memory-access requests from either the
RALU or the prefetch queue; queue requests always have priority. This queue is transparent to
the RALU and your software.
NOTE
When using a logic analyzer to debug code, remember that instructions are
preloaded into the prefetch queue and are not necessarily executed
immediately after they are fetched.
preloaded into the prefetch queue and are not necessarily executed
immediately after they are fetched.
When the bus controller receives a request from the queue, it fetches the code from the address
contained in the slave PC. The slave PC increases execution speed because the next instruction
byte is available immediately and the processor need not wait for the master PC to send the ad-
dress to the memory controller. If a jump, interrupt, call, or return changes the address sequence,
the master PC loads the new address into the slave PC, then the CPU flushes the queue and con-
tinues processing.
contained in the slave PC. The slave PC increases execution speed because the next instruction
byte is available immediately and the processor need not wait for the master PC to send the ad-
dress to the memory controller. If a jump, interrupt, call, or return changes the address sequence,
the master PC loads the new address into the slave PC, then the CPU flushes the queue and con-
tinues processing.
2.3.5
Interrupt Service
The microcontroller’s flexible interrupt-handling system has two main components: the program-
mable interrupt controller and the peripheral transaction server (PTS). The programmable inter-
rupt controller has a hardware priority scheme that can be modified by your software. Interrupts
that go through the interrupt controller are serviced by interrupt service routines that you provide.
The peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides
high-speed, low-overhead interrupt handling. You can configure most interrupts (except NMI,
trap, and unimplemented opcode) to be serviced by the PTS instead of the interrupt controller.
mable interrupt controller and the peripheral transaction server (PTS). The programmable inter-
rupt controller has a hardware priority scheme that can be modified by your software. Interrupts
that go through the interrupt controller are serviced by interrupt service routines that you provide.
The peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides
high-speed, low-overhead interrupt handling. You can configure most interrupts (except NMI,
trap, and unimplemented opcode) to be serviced by the PTS instead of the interrupt controller.
The PTS can transfer bytes or words, either individually or in blocks, between any memory loca-
tions, manage multiple analog-to-digital (A/D) conversions, and can generate pulse-width mod-
ulated (PWM) signals. The 8XC196MC and 8XC196MD have additional modes that allow
asynchronous or synchronous serial communication. PTS interrupts have a higher priority than
standard interrupts and may temporarily suspend interrupt service routines. See Chapter 5, “Stan-
dard and PTS Interrupts,” for more information.
tions, manage multiple analog-to-digital (A/D) conversions, and can generate pulse-width mod-
ulated (PWM) signals. The 8XC196MC and 8XC196MD have additional modes that allow
asynchronous or synchronous serial communication. PTS interrupts have a higher priority than
standard interrupts and may temporarily suspend interrupt service routines. See Chapter 5, “Stan-
dard and PTS Interrupts,” for more information.