Renesas R5S72641 User Manual
Section 19 Serial I/O with FIFO
Page 974 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(5) Transmit/Receive Reset
This module can separately reset the transmit and receive units by setting the following bits to 1.
Transmit reset: TXRST bit in SICTR
Receive reset: RXRST bit in SICTR
Table 19.10 shows the details of initialization upon the transmit or receive reset.
Receive reset: RXRST bit in SICTR
Table 19.10 shows the details of initialization upon the transmit or receive reset.
Table 19.10 Transmit and Receive Reset
Type Objects
Initialized
Transmit reset
SITDR
Valid data in transmit FIFO
The TFEMP and TDREQ bits in SISTR
The TXE bit in SICTR
Receive reset
SIRDR
Valid data in receive FIFO
The RFFUL and RDREQ bits in SISTR
The RXE bit in SICTR